| Message ID | 20240423-usb-phy-gs101-v1-1-ebdcb3ac174d@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | USB31DRD phy support for Google Tensor gs101 (HS & SS) | expand |
On Tue, Apr 23, 2024 at 06:06:03PM +0100, André Draszik wrote: > Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor > gs101 SoC. > > It needs additional clocks enabled for register access, and additional > memory regions (PCS & PMA) are required for successful configuration. > > Signed-off-by: André Draszik <andre.draszik@linaro.org> > --- > .../bindings/phy/samsung,usb3-drd-phy.yaml | 78 +++++++++++++++++----- > 1 file changed, 61 insertions(+), 17 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml > index 452e584d9812..db1dc4c60b72 100644 > --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml > @@ -25,6 +25,7 @@ description: | > properties: > compatible: > enum: > + - google,gs101-usb31drd-phy > - samsung,exynos5250-usbdrd-phy > - samsung,exynos5420-usbdrd-phy > - samsung,exynos5433-usbdrd-phy > @@ -57,7 +58,18 @@ properties: > the OF graph bindings specified. > > reg: > - maxItems: 1 > + minItems: 1 > + items: > + - description: PHY register base address. > + - description: PCS register base address. > + - description: PMA register base address. > + > + reg-names: > + minItems: 1 > + items: > + - const: phy > + - const: pcs > + - const: pma > > samsung,pmu-syscon: > $ref: /schemas/types.yaml#/definitions/phandle > @@ -85,30 +97,62 @@ allOf: > properties: > compatible: > contains: > - enum: > - - samsung,exynos5433-usbdrd-phy > - - samsung,exynos7-usbdrd-phy > + const: google,gs101-usb31drd-phy > then: > properties: > clocks: > - minItems: 5 > - maxItems: 5 > - clock-names: > items: > - - const: phy > - - const: ref > - - const: phy_utmi > - - const: phy_pipe > - - const: itp > - else: > - properties: > - clocks: > - minItems: 2 > - maxItems: 2 > + - description: Gate of main PHY clock > + - description: Gate of PHY reference clock > + - description: Gate of control interface AXI clock > + - description: Gate of control interface APB clock > + - description: Gate of SCL APB clock > clock-names: > items: > - const: phy > - const: ref > + - const: ctrl_aclk > + - const: ctrl_pclk > + - const: scl_pclk > + reg: > + minItems: 3 > + reg-names: > + minItems: 3 > + required: > + - reg-names > + else: > + if: We generally try to avoid having nested else/if like this. Please change the existing 'else' to an 'if' and then add an 'if' for your new compatible. Rob
diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 452e584d9812..db1dc4c60b72 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -25,6 +25,7 @@ description: | properties: compatible: enum: + - google,gs101-usb31drd-phy - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy @@ -57,7 +58,18 @@ properties: the OF graph bindings specified. reg: - maxItems: 1 + minItems: 1 + items: + - description: PHY register base address. + - description: PCS register base address. + - description: PMA register base address. + + reg-names: + minItems: 1 + items: + - const: phy + - const: pcs + - const: pma samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle @@ -85,30 +97,62 @@ allOf: properties: compatible: contains: - enum: - - samsung,exynos5433-usbdrd-phy - - samsung,exynos7-usbdrd-phy + const: google,gs101-usb31drd-phy then: properties: clocks: - minItems: 5 - maxItems: 5 - clock-names: items: - - const: phy - - const: ref - - const: phy_utmi - - const: phy_pipe - - const: itp - else: - properties: - clocks: - minItems: 2 - maxItems: 2 + - description: Gate of main PHY clock + - description: Gate of PHY reference clock + - description: Gate of control interface AXI clock + - description: Gate of control interface APB clock + - description: Gate of SCL APB clock clock-names: items: - const: phy - const: ref + - const: ctrl_aclk + - const: ctrl_pclk + - const: scl_pclk + reg: + minItems: 3 + reg-names: + minItems: 3 + required: + - reg-names + else: + if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-usbdrd-phy + - samsung,exynos7-usbdrd-phy + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: phy + - const: ref + - const: phy_utmi + - const: phy_pipe + - const: itp + reg: + maxItems: 1 + else: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: phy + - const: ref + reg: + maxItems: 1 additionalProperties: false
Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor gs101 SoC. It needs additional clocks enabled for register access, and additional memory regions (PCS & PMA) are required for successful configuration. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 78 +++++++++++++++++----- 1 file changed, 61 insertions(+), 17 deletions(-)