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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id t22-20020a1709063e5600b00a5209dc79c1sm7351624eji.146.2024.04.23.10.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 10:06:24 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 23 Apr 2024 18:06:03 +0100 Subject: [PATCH 1/7] dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-usb-phy-gs101-v1-1-ebdcb3ac174d@linaro.org> References: <20240423-usb-phy-gs101-v1-0-ebdcb3ac174d@linaro.org> In-Reply-To: <20240423-usb-phy-gs101-v1-0-ebdcb3ac174d@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar , Sam Protsenko Cc: Krzysztof Kozlowski , Tudor Ambarus , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= X-Mailer: b4 0.12.4 Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor gs101 SoC. It needs additional clocks enabled for register access, and additional memory regions (PCS & PMA) are required for successful configuration. Signed-off-by: André Draszik --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 78 +++++++++++++++++----- 1 file changed, 61 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 452e584d9812..db1dc4c60b72 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -25,6 +25,7 @@ description: | properties: compatible: enum: + - google,gs101-usb31drd-phy - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy @@ -57,7 +58,18 @@ properties: the OF graph bindings specified. reg: - maxItems: 1 + minItems: 1 + items: + - description: PHY register base address. + - description: PCS register base address. + - description: PMA register base address. + + reg-names: + minItems: 1 + items: + - const: phy + - const: pcs + - const: pma samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle @@ -85,30 +97,62 @@ allOf: properties: compatible: contains: - enum: - - samsung,exynos5433-usbdrd-phy - - samsung,exynos7-usbdrd-phy + const: google,gs101-usb31drd-phy then: properties: clocks: - minItems: 5 - maxItems: 5 - clock-names: items: - - const: phy - - const: ref - - const: phy_utmi - - const: phy_pipe - - const: itp - else: - properties: - clocks: - minItems: 2 - maxItems: 2 + - description: Gate of main PHY clock + - description: Gate of PHY reference clock + - description: Gate of control interface AXI clock + - description: Gate of control interface APB clock + - description: Gate of SCL APB clock clock-names: items: - const: phy - const: ref + - const: ctrl_aclk + - const: ctrl_pclk + - const: scl_pclk + reg: + minItems: 3 + reg-names: + minItems: 3 + required: + - reg-names + else: + if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-usbdrd-phy + - samsung,exynos7-usbdrd-phy + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: phy + - const: ref + - const: phy_utmi + - const: phy_pipe + - const: itp + reg: + maxItems: 1 + else: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: phy + - const: ref + reg: + maxItems: 1 additionalProperties: false