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AJvYcCWf/yIvNdb1vIjC7n8gEhFE//WtTTmRIL4rcTt2YyvKMLGlRMCW8dxLI8jTjBYmkC1yY3U6NjwLctmBI6RNTBZWoRYM4qJXvitcG/6PTKcUZ8w= X-Gm-Message-State: AOJu0YwkThGT5ZeteV8dWaNUreuB8HguF7CWJU9c7/Ukfj6S3C+kWN6r Vg5HkkgFVIlz6D6F5X+Hb2FMQO46xELDEjTY0MLt4x/j5XaOb/ys8f/HEuDXsd0= X-Google-Smtp-Source: AGHT+IGaC6Vi359eexueF4iWi9nmGX5wxuCM1Fm/OruWavgWB268ofzG0ipJO8D32PKK0SvENR0WUA== X-Received: by 2002:a05:600c:2991:b0:418:9d5a:f680 with SMTP id r17-20020a05600c299100b004189d5af680mr254261wmd.25.1713905429971; Tue, 23 Apr 2024 13:50:29 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:4269:2542:5a09:9ca1]) by smtp.gmail.com with ESMTPSA id bg5-20020a05600c3c8500b00419f419236fsm13065443wmb.41.2024.04.23.13.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 13:50:29 -0700 (PDT) From: Peter Griffin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, jejb@linux.ibm.com, martin.petersen@oracle.com, James.Bottomley@HansenPartnership.com, ebiggers@kernel.org Cc: linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v2 09/14] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option Date: Tue, 23 Apr 2024 21:50:01 +0100 Message-ID: <20240423205006.1785138-10-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240423205006.1785138-1-peter.griffin@linaro.org> References: <20240423205006.1785138-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This option is intended to be set for SoCs that have HCI_V2P1_CTRL register and can select their tick source via IA_TICK_SEL bit. Source clock selection for timer tick 0x0 = Bus clock (aclk) 0x1 = Function clock (mclk) Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 9 +++++++++ drivers/ufs/host/ufs-exynos.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 66e52c3607e2..66093a905986 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -50,6 +50,8 @@ #define HCI_ERR_EN_N_LAYER 0x80 #define HCI_ERR_EN_T_LAYER 0x84 #define HCI_ERR_EN_DME_LAYER 0x88 +#define HCI_V2P1_CTRL 0x8C +#define IA_TICK_SEL BIT(16) #define HCI_CLKSTOP_CTRL 0xB0 #define REFCLKOUT_STOP BIT(4) #define MPHY_APBCLK_STOP BIT(3) @@ -1005,6 +1007,13 @@ static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) { u32 val; + /* Select function clock (mclk) for timer tick */ + if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { + val = hci_readl(ufs, HCI_V2P1_CTRL); + val |= IA_TICK_SEL; + hci_writel(ufs, val, HCI_V2P1_CTRL); + } + val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); } diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 0fc21b6bbfcd..acf07cc54684 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -222,6 +222,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) #define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) +#define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7) }; #define for_each_ufs_rx_lane(ufs, i) \