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AJvYcCWPDSjFrkl6vyy4JXlU77dcR//ZPpBWi0BNsgN7Er+oTdV5hzuNKbTfNEa6/ktTZ/in+r0ohijrfEhlaShd8549uR7CkBzQNDDlywEj7QyXb24= X-Gm-Message-State: AOJu0Yx0Hm6bstXiSn0rUFatdHfv1D2tzzO8zD+EmF7Ot3b4ydVqscmY 7Tow41Oh2Qg2nd2P/qowvcf4vuhLhwL60Ty5u3OVOG5UtLTlrfK8xvHfuAGdj48= X-Google-Smtp-Source: AGHT+IH6z+0zlU25050wMvD0vuxotNnh43coyHQIMqF5YmCpBQNXBCfzRnt18Ll4b9pvC+KY+bIGQA== X-Received: by 2002:a05:600c:4590:b0:418:f991:713f with SMTP id r16-20020a05600c459000b00418f991713fmr263623wmo.23.1713905431899; Tue, 23 Apr 2024 13:50:31 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:4269:2542:5a09:9ca1]) by smtp.gmail.com with ESMTPSA id bg5-20020a05600c3c8500b00419f419236fsm13065443wmb.41.2024.04.23.13.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 13:50:31 -0700 (PDT) From: Peter Griffin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, jejb@linux.ibm.com, martin.petersen@oracle.com, James.Bottomley@HansenPartnership.com, ebiggers@kernel.org Cc: linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, Peter Griffin , Krzysztof Kozlowski Subject: [PATCH v2 10/14] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz Date: Tue, 23 Apr 2024 21:50:02 +0100 Message-ID: <20240423205006.1785138-11-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240423205006.1785138-1-peter.griffin@linaro.org> References: <20240423205006.1785138-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Platforms such as Tensor gs101 the pclk frequency is 267Mhz. Increase PCLK_AVAIL_MAX so we don't fail the frequency check. Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index acf07cc54684..7acc13914100 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -116,7 +116,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 167000000 +#define PCLK_AVAIL_MAX 267000000 struct exynos_ufs_uic_attr { /* TX Attributes */