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[178.122.232.167]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-57cb72da156sm7731278a12.22.2024.06.18.06.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 06:59:51 -0700 (PDT) From: Dzmitry Sankouski Date: Tue, 18 Jun 2024 16:59:36 +0300 Subject: [PATCH v3 02/23] gcc-sdm845: Add rates to the GP clocks Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240618-starqltechn_integration_upstream-v3-2-e3f6662017ac@gmail.com> References: <20240618-starqltechn_integration_upstream-v3-0-e3f6662017ac@gmail.com> In-Reply-To: <20240618-starqltechn_integration_upstream-v3-0-e3f6662017ac@gmail.com> To: Sebastian Reichel , Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Dmitry Torokhov , Pavel Machek , Liam Girdwood , Mark Brown , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Krzysztof Kozlowski , Konrad Dybcio , Chanwoo Choi , phone-devel@vger.kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-input@vger.kernel.org, linux-leds@vger.kernel.org, linux-pwm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Dzmitry Sankouski X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718719184; l=1529; i=dsankouski@gmail.com; s=20240618; h=from:subject:message-id; bh=3HcxN0k0ztF3vxPnK9xWSo9UBEsozU7BSPW6y11+ONM=; b=FrDsj3ETUaVVQUOm6LFM6D0nBF+hdet963cj5SLvZ7Hei+IvuV6/EU9kWQmVy5U92Zb8ZIbV0 dOFifsD41gAC/4qNSbNS6FuI5+bBgsoWvtPrvXOm97raYLyZG5Ds/10 X-Developer-Key: i=dsankouski@gmail.com; a=ed25519; pk=6pMMVVDDReSiRgPCbMOUauN5nS3ty4Sf5b7a2gi4x0M= sdm845 has "General Purpose" clocks that can be muxed to SoC pins. Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks) Signed-off-by: Dzmitry Sankouski --- drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index ea4c3bf4fb9b..0efd3364e8f5 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -283,7 +283,21 @@ static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * See comment in gcc-mam8916.c at ftbl_gcc_gp1_3_clk. + */ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(10000, P_BI_TCXO, 16, 1, 120), + F(20000, P_BI_TCXO, 16, 1, 60), + F(100000, P_BI_TCXO, 16, 1, 12), + F(500000, P_GPLL0_OUT_EVEN, 12, 1, 100), + F(1000000, P_GPLL0_OUT_EVEN, 12, 1, 50), + F(2500000, P_GPLL0_OUT_EVEN, 12, 1, 10), + F(5000000, P_GPLL0_OUT_EVEN, 12, 1, 5), F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),