| Message ID | 20241204122335.1578-1-faraz.ata@samsung.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: exynosautov920: add DMA nodes | expand |
Hi Faraz, > -----Original Message----- > From: Faraz Ata <faraz.ata@samsung.com> > Sent: Wednesday, December 4, 2024 5:54 PM > To: devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org; > krzk+dt@kernel.org; robh@kernel.org > Cc: linux-arm-kernel@lists.infradead.org; alim.akhtar@samsung.com; > rosa.pila@samsung.com; Faraz Ata <faraz.ata@samsung.com> > Subject: [PATCH] arm64: dts: exynosautov920: add DMA nodes > > ExynosAutov920 SoC has 7 DMA controllers. Two secure DMAC > (SPDMA0 & SPDMA1) and five non-secure DMAC (PDMA0 to PDMA4). > Adds the required dt node for the same. > > Signed-off-by: Faraz Ata <faraz.ata@samsung.com> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 63 > +++++++++++++++++++ > 1 file changed, 63 insertions(+) > . . . > 2.34.1
On 04/12/2024 13:23, Faraz Ata wrote: > + > + spdma1: dma-controller@10190000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x10190000 0x1000>; > + interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; > + clock-names = "apb_pclk"; > + #dma-cells = <1>; > + }; > + > + pdma0: dma-controller@101A0000 { Please do not send downstream code directly, but fix it to match upstream. Lowercase hex everywhere. Best regards, Krzysztof
On 12/4/24 12:23 PM, Faraz Ata wrote: > ExynosAutov920 SoC has 7 DMA controllers. Two secure DMAC > (SPDMA0 & SPDMA1) and five non-secure DMAC (PDMA0 to PDMA4). > Adds the required dt node for the same. typos: s/adds/add, s/node/nodes Hi, Faraz! Have you tested DMA on ExynosAutov920, did it work with the upstream driver code? I tried enabling it for GS101 and I had some questions that I couldn't answer, and I moved forward in the meantime. Would you mind taking a look at: https://lore.kernel.org/linux-arm-kernel/e4089855-aca9-4993-bac6-e59370cf7954@linaro.org/ Thanks a ton! ta
Hi Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, December 9, 2024 1:04 PM > To: Faraz Ata <faraz.ata@samsung.com>; devicetree@vger.kernel.org; linux- > samsung-soc@vger.kernel.org; krzk+dt@kernel.org; robh@kernel.org > Cc: linux-arm-kernel@lists.infradead.org; alim.akhtar@samsung.com; > rosa.pila@samsung.com > Subject: Re: [PATCH] arm64: dts: exynosautov920: add DMA nodes > > On 04/12/2024 13:23, Faraz Ata wrote: > > + > > + spdma1: dma-controller@10190000 { > > + compatible = "arm,pl330", "arm,primecell"; > > + reg = <0x10190000 0x1000>; > > + interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cmu_misc > CLK_MOUT_MISC_NOC_USER>; > > + clock-names = "apb_pclk"; > > + #dma-cells = <1>; > > + }; > > + > > + pdma0: dma-controller@101A0000 { > > Please do not send downstream code directly, but fix it to match upstream. > Lowercase hex everywhere. > Thanks for your review, will takecare in future patches. > Best regards, > Krzysztof
Hi Tudor > -----Original Message----- > From: Tudor Ambarus <tudor.ambarus@linaro.org> > Sent: Monday, December 9, 2024 1:13 PM > To: Faraz Ata <faraz.ata@samsung.com>; devicetree@vger.kernel.org; linux- > samsung-soc@vger.kernel.org; krzk+dt@kernel.org; robh@kernel.org > Cc: linux-arm-kernel@lists.infradead.org; alim.akhtar@samsung.com; > rosa.pila@samsung.com; Peter Griffin <peter.griffin@linaro.org>; André > Draszik <andre.draszik@linaro.org>; William McVicker > <willmcvicker@google.com>; kernel-team@android.com > Subject: Re: [PATCH] arm64: dts: exynosautov920: add DMA nodes > > > > On 12/4/24 12:23 PM, Faraz Ata wrote: > > ExynosAutov920 SoC has 7 DMA controllers. Two secure DMAC > > (SPDMA0 & SPDMA1) and five non-secure DMAC (PDMA0 to PDMA4). > > Adds the required dt node for the same. > > typos: s/adds/add, s/node/nodes > Thanks for your review, will correct in the v2 > Hi, Faraz! > > Have you tested DMA on ExynosAutov920, did it work with the upstream > driver code? > Yes, I tested with dmatest for M2M for all channel, it is working as expected with mainline PL330 driver. > I tried enabling it for GS101 and I had some questions that I couldn't answer, > and I moved forward in the meantime. Would you mind taking a look at: > > https://lore.kernel.org/linux-arm-kernel/e4089855-aca9-4993-bac6- > e59370cf7954@linaro.org/ > I am not sure about GS101 architecture, will try to reachout internally to people who might be aware of this. > Thanks a ton! > ta
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index c759134c909e..e65be0c97f7e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -193,6 +193,69 @@ gic: interrupt-controller@10400000 { interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + spdma0: dma-controller@10180000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10180000 0x1000>; + interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + spdma1: dma-controller@10190000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10190000 0x1000>; + interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma0: dma-controller@101A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x101A0000 0x1000>; + interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@101B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x101B0000 0x1000>; + interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma2: dma-controller@101C0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x101C0000 0x1000>; + interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma3: dma-controller@101D0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x101D0000 0x1000>; + interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma4: dma-controller@101E0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x101E0000 0x1000>; + interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + cmu_peric0: clock-controller@10800000 { compatible = "samsung,exynosautov920-cmu-peric0"; reg = <0x10800000 0x8000>;
ExynosAutov920 SoC has 7 DMA controllers. Two secure DMAC (SPDMA0 & SPDMA1) and five non-secure DMAC (PDMA0 to PDMA4). Adds the required dt node for the same. Signed-off-by: Faraz Ata <faraz.ata@samsung.com> --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+)