| Message ID | 20241205-gs101-phy-lanes-orientation-phy-v3-5-32f721bed219@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm) | expand |
On Thu, Dec 05, 2024 at 07:33:16AM +0000, André Draszik wrote: > We currently don't gate the power to the SS phy in phy_exit(). > > Shuffle the code slightly to ensure the power is gated to the SS phy as > well. > > Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)") > CC: stable@vger.kernel.org # 6.11+ Why is a patch 5/8 a stable thing? If this is such an important bugfix, it should be sent separately as a 1/1 patch, right? thanks, greg k-h
On 05-12-24, 09:04, Greg KH wrote: > On Thu, Dec 05, 2024 at 07:33:16AM +0000, André Draszik wrote: > > We currently don't gate the power to the SS phy in phy_exit(). > > > > Shuffle the code slightly to ensure the power is gated to the SS phy as > > well. > > > > Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)") > > CC: stable@vger.kernel.org # 6.11+ > > Why is a patch 5/8 a stable thing? If this is such an important bugfix, > it should be sent separately as a 1/1 patch, right? Correct, one should move fixes to top of the series..
Hi Vinod, On Sun, 2024-12-08 at 21:09 +0530, Vinod Koul wrote: > On 05-12-24, 09:04, Greg KH wrote: > > On Thu, Dec 05, 2024 at 07:33:16AM +0000, André Draszik wrote: > > > We currently don't gate the power to the SS phy in phy_exit(). > > > > > > Shuffle the code slightly to ensure the power is gated to the SS phy as > > > well. > > > > > > Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)") > > > CC: stable@vger.kernel.org # 6.11+ > > > > Why is a patch 5/8 a stable thing? If this is such an important bugfix, > > it should be sent separately as a 1/1 patch, right? > > Correct, one should move fixes to top of the series.. Thanks Vinod, and sorry for that - separated out as per Greg's request here: https://lore.kernel.org/all/20241205-gs101-usb-phy-fix-v4-1-0278809fb810@linaro.org/ Cheers, Andre'
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 2a724d362c2d..c1ce6fdeef31 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1296,14 +1296,17 @@ static int exynos5_usbdrd_gs101_phy_exit(struct phy *phy) struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); int ret; + if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { + ret = exynos850_usbdrd_phy_exit(phy); + if (ret) + return ret; + } + + exynos5_usbdrd_phy_isol(inst, true); + if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI) return 0; - ret = exynos850_usbdrd_phy_exit(phy); - if (ret) - return ret; - - exynos5_usbdrd_phy_isol(inst, true); return regulator_bulk_disable(phy_drd->drv_data->n_regulators, phy_drd->regulators); }
We currently don't gate the power to the SS phy in phy_exit(). Shuffle the code slightly to ensure the power is gated to the SS phy as well. Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)") CC: stable@vger.kernel.org # 6.11+ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> --- v2: * add cc-stable and fixes tags (Krzysztof) * collect tags --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)