diff mbox series

ARM: cacheinfo fix format field mask

Message ID 20250115-arm-cacheinfo-fix-v1-1-5f30eeb4e463@linaro.org (mailing list archive)
State New
Headers show
Series ARM: cacheinfo fix format field mask | expand

Commit Message

Dmitry Baryshkov Jan. 15, 2025, 11:10 a.m. UTC 
Fix C&P error left unnoticed during the reviews. The FORMAT field spans
over bits 29-31, not 24-27 of the CTR register.

Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/kernel/cacheinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


---
base-commit: e7bb221a638962d487231ac45a6699fb9bb8f9fa
change-id: 20250115-arm-cacheinfo-fix-9ee32f3a5e34

Best regards,
diff mbox series

Patch

diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c
index a8eabcaa18d8941ce31ad267ce0d369b8d53886a..e1469b6417804d2802e847031950cb99b7b4e1d2 100644
--- a/arch/arm/kernel/cacheinfo.c
+++ b/arch/arm/kernel/cacheinfo.c
@@ -23,7 +23,7 @@ 
 
 #define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
 
-#define CTR_FORMAT_MASK	GENMASK(27, 24)
+#define CTR_FORMAT_MASK	GENMASK(31, 29)
 #define CTR_FORMAT_ARMV6 0
 #define CTR_FORMAT_ARMV7 4
 #define CTR_CWG_MASK	GENMASK(27, 24)