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Wed, 15 Jan 2025 03:10:49 -0800 (PST) From: Dmitry Baryshkov Date: Wed, 15 Jan 2025 13:10:49 +0200 Subject: [PATCH] ARM: cacheinfo fix format field mask Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250115-arm-cacheinfo-fix-v1-1-5f30eeb4e463@linaro.org> X-B4-Tracking: v=1; b=H4sIALiXh2cC/x2MOwqAMBAFryJbu5CPKfQqYhHii25hIgmIIN7dY DkDMw9VFEGlqXuo4JIqOTXQfUdh92kDy9qYjDJOae3Yl4ODDzskxcxRbh4Ba6L1Dnag1p0FTf/ PeXnfDxqi6kRjAAAA X-Change-ID: 20250115-arm-cacheinfo-fix-9ee32f3a5e34 To: Russell King , Linus Walleij , Sudeep Holla , Ard Biesheuvel , "Russell King (Oracle)" Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Marek Szyprowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1187; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Dt8d1C/tljuHwCYE9rqB9mV99qR1IwA31kMWM8oW5ys=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnh5e5bVtlXo43+ur9ZmjVXRM38owhcLp66/0P/ 3imQJL3v1iJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ4eXuQAKCRCLPIo+Aiko 1eGACACSCS9TEYuK7peyrjK8tniNVAB6t+KYUw+pzBOFimWNqyFNHEUbE2NyhIItTO3hUjmAa9A +aaL8HtMbRTwNf74A8MI1AGnEzYmc+chnIgDMO17jjAdpOqZrcoKqAahQC30eu7hkTgWyULad+O s9xmvRtr0Yd93LFs7pvflaqFcpBk0NmibgCh0DC211VjKq9ka5S1wFkrIhYdIEcMxp2GIZjJX2O f8Zhwfl5CHApOncr0wYBSMGx0BqLodP27M97P7W8Cs35CTbY+qnNMTphkzZjEwGkhQfu0hRswte X7xGLnxVgBocaKqQ35BM4T4yYK5BF/sstqu69VSR1sQJ6GIi X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Fix C&P error left unnoticed during the reviews. The FORMAT field spans over bits 29-31, not 24-27 of the CTR register. Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support") Reported-by: Marek Szyprowski Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/ Signed-off-by: Dmitry Baryshkov --- arch/arm/kernel/cacheinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: e7bb221a638962d487231ac45a6699fb9bb8f9fa change-id: 20250115-arm-cacheinfo-fix-9ee32f3a5e34 Best regards, diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c index a8eabcaa18d8941ce31ad267ce0d369b8d53886a..e1469b6417804d2802e847031950cb99b7b4e1d2 100644 --- a/arch/arm/kernel/cacheinfo.c +++ b/arch/arm/kernel/cacheinfo.c @@ -23,7 +23,7 @@ #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -#define CTR_FORMAT_MASK GENMASK(27, 24) +#define CTR_FORMAT_MASK GENMASK(31, 29) #define CTR_FORMAT_ARMV6 0 #define CTR_FORMAT_ARMV7 4 #define CTR_CWG_MASK GENMASK(27, 24)