pinctrl: samsung: Save/restore eint_mask over suspend for EINT_TYPE GPIOs

Commit Message

Jonathan Bakker April 25, 2020, 11:10 p.m. UTC

Currently, for EINT_TYPE GPIOs, the CON and FLTCON registers
are saved and restored over a suspend/resume cycle.  However, the
EINT_MASK registers are not.

On S5PV210 at the very least, these registers are not retained over
suspend, leading to the interrupts remaining masked upon resume and
therefore no interrupts being triggered for the device.  There should
be no effect on any SoCs that do retain these registers as theoretically
we would just be re-writing what was already there.

Signed-off-by: Jonathan Bakker <[e-mail]>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Krzysztof Kozlowski April 28, 2020, 9:40 a.m. UTC | #1

On Sat, Apr 25, 2020 at 04:10:46PM -0700, Jonathan Bakker wrote:
> Currently, for EINT_TYPE GPIOs, the CON and FLTCON registers
> are saved and restored over a suspend/resume cycle.  However, the
> EINT_MASK registers are not.
> 
> On S5PV210 at the very least, these registers are not retained over
> suspend, leading to the interrupts remaining masked upon resume and
> therefore no interrupts being triggered for the device.  There should
> be no effect on any SoCs that do retain these registers as theoretically
> we would just be re-writing what was already there.
> 
> Signed-off-by: Jonathan Bakker <[e-mail]>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

Exynos4412 (Odroid U3) also did not retain the register values. SD card
detect interrupt should be affected.

Thanks, applied (with CC-stable).

Best regards,
Krzysztof

Patch

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 0599f5127b01..e6ddb54afaf2 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -265,6 +265,7 @@  struct exynos_eint_gpio_save {
 	u32 eint_con;
 	u32 eint_fltcon0;
 	u32 eint_fltcon1;
+	u32 eint_mask;
 };
 
 /*
@@ -608,10 +609,13 @@  static void exynos_pinctrl_suspend_bank(
 						+ 2 * bank->eint_offset);
 	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 						+ 2 * bank->eint_offset + 4);
+	save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+						+ bank->eint_offset);
 
 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
 	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
 	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
+	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);
 }
 
 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
@@ -653,6 +657,9 @@  static void exynos_pinctrl_resume_bank(
 	pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
 			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
+	pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
+			readl(regs + bank->irq_chip->eint_mask
+			+ bank->eint_offset), save->eint_mask);
 
 	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
 						+ bank->eint_offset);
@@ -660,6 +667,8 @@  static void exynos_pinctrl_resume_bank(
 						+ 2 * bank->eint_offset);
 	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 						+ 2 * bank->eint_offset + 4);
+	writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+						+ bank->eint_offset);
 }
 
 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)