From patchwork Thu Jul 7 10:01:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 9218733 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8FFA260574 for ; Thu, 7 Jul 2016 10:02:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8276B28814 for ; Thu, 7 Jul 2016 10:02:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7770228818; Thu, 7 Jul 2016 10:02:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8820C28814 for ; Thu, 7 Jul 2016 10:02:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933468AbcGGKCY (ORCPT ); Thu, 7 Jul 2016 06:02:24 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:52474 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751920AbcGGKCW (ORCPT ); Thu, 7 Jul 2016 06:02:22 -0400 Received: from [137.158.23.252] (helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2) (envelope-from ) id 1bL68N-00018N-9U; Thu, 07 Jul 2016 10:02:16 +0000 Received: from broonie by finisterre with local (Exim 4.87) (envelope-from ) id 1bL682-0000ul-2D; Thu, 07 Jul 2016 12:01:54 +0200 From: Mark Brown To: Andi Shyti Cc: Sylwester Nawrocki , Mark Brown , Mark Brown , Sylwester Nawrocki , Kukjin Kim , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Andi Shyti , linux-spi@vger.kernel.org In-Reply-To: <1467876237-12183-1-git-send-email-andi.shyti@samsung.com> Message-Id: Date: Thu, 07 Jul 2016 12:01:54 +0200 X-SA-Exim-Connect-IP: 137.158.23.252 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Applied "spi: s3c64xx: do not disable the clock while configuring the spi" to the spi tree X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: s3c64xx: do not disable the clock while configuring the spi has been applied to the spi tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From d9aaf1dc984a448ae5630e53a611a8b3489d1f8d Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Thu, 7 Jul 2016 16:23:57 +0900 Subject: [PATCH] spi: s3c64xx: do not disable the clock while configuring the spi When the clock is coming from the cmu it is not required to be disabled and then re-enabled in order to change the rate. Besides, some exynos chipsets (e.g. exynos5433) do not deliver any to the SFR if one from the pclk ("spi" in this case) or sclk ("busclk") is disabled. Remove the clock disabling/enabling to avoid falling into this situation. Signed-off-by: Sylwester Nawrocki Signed-off-by: Andi Shyti Signed-off-by: Mark Brown --- drivers/spi/spi-s3c64xx.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 9f0119f64f93..df88fa161d8a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -596,9 +596,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) u32 val; /* Disable Clock */ - if (sdd->port_conf->clk_from_cmu) { - clk_disable_unprepare(sdd->src_clk); - } else { + if (!sdd->port_conf->clk_from_cmu) { val = readl(regs + S3C64XX_SPI_CLK_CFG); val &= ~S3C64XX_SPI_ENCLK_ENABLE; writel(val, regs + S3C64XX_SPI_CLK_CFG); @@ -641,11 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { - /* Configure Clock */ - /* There is half-multiplier before the SPI */ clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); - /* Enable Clock */ - clk_prepare_enable(sdd->src_clk); } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG);