From patchwork Mon Nov 6 17:20:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sathya Prakash Veerichetty X-Patchwork-Id: 10043901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8E1B9603FF for ; Mon, 6 Nov 2017 17:20:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71C06293C0 for ; Mon, 6 Nov 2017 17:20:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6687929F22; Mon, 6 Nov 2017 17:20:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9777F293C0 for ; Mon, 6 Nov 2017 17:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932460AbdKFRU1 (ORCPT ); Mon, 6 Nov 2017 12:20:27 -0500 Received: from mail-qk0-f193.google.com ([209.85.220.193]:43732 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932083AbdKFRU0 (ORCPT ); Mon, 6 Nov 2017 12:20:26 -0500 Received: by mail-qk0-f193.google.com with SMTP id 78so4911867qkz.0 for ; Mon, 06 Nov 2017 09:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:references:in-reply-to:mime-version:thread-index:date :message-id:subject:to:cc; bh=PpOWGqGdNRsIMUcfLzYBZCOsRfyRXSNh2Yv+CEDqgUo=; b=BpOg2fIcLzAWf1bzXPFqImJUDYGgFfr02ELaNCJGfJO4u9My4xe8JGtmTkXOhmxTzy z6DLtqaxPVEm3OFEWOq5AMJIPYythyfRGIaO8JBlPGIowBb4DhNYJHMxMUdi8kcYydI/ GylLYGWZIwscGLvtRDPsqoHcz3pOrTO/YO+3Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:references:in-reply-to:mime-version :thread-index:date:message-id:subject:to:cc; bh=PpOWGqGdNRsIMUcfLzYBZCOsRfyRXSNh2Yv+CEDqgUo=; b=smwUtWBFvnklgQNguxNUD8ycKn3hmknRpx+I1wW48cVDuYRcvCy7KBdsxOmrvM52Kp 50RRM9JO9Hnq1KcHsvctzVdYIWJFu+3D2TBXSzb/n0d7yQVTg5xGxW+SyO1Nxw5cDGAA MXe0njDi3KlK6yWfw2bvKRpp/BJdKoxXugGXpgwCDeD2+kkodpFestkR70wzuJ4gSx/G 8qshHLAL4jyrDTJTNzD81XskG3TYEbj8O6d9q0Hq2v2MaqyN/uGzafFYuCOHM07bBxMs ia70DG0gKiwEDdR0qhtugaICTLejp8b7P6f3paWVRSsQ7HeoQr8Iyc7y8EZjLgXoT6OQ XYhQ== X-Gm-Message-State: AMCzsaVXa1KU9EERwnfQ53L63vSs6wr09nFdL9GM+uaEWQkwHLcDA7/z hfLd/WG9XnnIhTHfFLsZp+GyG1JsVaMKswTMS8H4 X-Google-Smtp-Source: ABhQp+TUyYVofq6mf7twbxRgRRlNbz6kXCQO8pbHhWEp37+RsuCvH7cuYL6hii4Zvb5QfhfkOh036LP1ujKg1mSchVo= X-Received: by 10.55.76.67 with SMTP id z64mr23542820qka.346.1509988825127; Mon, 06 Nov 2017 09:20:25 -0800 (PST) From: Sathya Prakash Veerichetty References: <20171106133540.506572-1-arnd@arndb.de> In-Reply-To: <20171106133540.506572-1-arnd@arndb.de> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 14.0 Thread-Index: AQGk08QODFcPZrzPgkY3Sh0+oq0Y2KNkn2wQ Date: Mon, 6 Nov 2017 10:20:24 -0700 Message-ID: <0083105ba2839c710c6455356c7e4086@mail.gmail.com> Subject: RE: [PATCH] mpt3sas: fix dma_addr_t casts To: Arnd Bergmann , Chaitra Basappa , Suganath Prabu Subramani , "James E.J. Bottomley" , "Martin K. Petersen" Cc: Tomas Henzl , Sreekanth Reddy , Hannes Reinecke , Romain Perier , James Bottomley , Bart Van Assche , PDL-MPT-FUSIONLINUX , linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Acked-by: Sathya Prakash Veerichetty -----Original Message----- From: Arnd Bergmann [mailto:arnd@arndb.de] Sent: Monday, November 6, 2017 6:35 AM To: Sathya Prakash; Chaitra P B; Suganath Prabu Subramani; James E.J. Bottomley; Martin K. Petersen Cc: Arnd Bergmann; Tomas Henzl; Sreekanth Reddy; Hannes Reinecke; Romain Perier; James Bottomley; Bart Van Assche; MPT-FusionLinux.pdl@broadcom.com; linux-scsi@vger.kernel.org; linux-kernel@vger.kernel.org Subject: [PATCH] mpt3sas: fix dma_addr_t casts The newly added base_make_prp_nvme function triggers a build warning on some 32-bit configurations: drivers/scsi/mpt3sas/mpt3sas_base.c: In function 'base_make_prp_nvme': drivers/scsi/mpt3sas/mpt3sas_base.c:1664:13: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] msg_phys = (dma_addr_t)mpt3sas_base_get_pcie_sgl_dma(ioc, smid); After taking a closer look, I found that the problem is that the new code mixes up pointers and dma_addr_t values unnecessarily. This changes it to use the correct types consistently, which lets us get rid of a lot of type casts in the process. I'm also renaming some variables to avoid confusion between physical and dma address spaces that are often distinct. Fixes: 016d5c35e278 ("scsi: mpt3sas: SGL to PRP Translation for I/Os to NVMe devices") Signed-off-by: Arnd Bergmann --- drivers/scsi/mpt3sas/mpt3sas_base.c | 62 +++++++++++++++++-------------------- drivers/scsi/mpt3sas/mpt3sas_base.h | 2 +- 2 files changed, 30 insertions(+), 34 deletions(-) /* hi-priority queue */ -- 2.9.0 diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 7a3f4d14f260..8027de465d47 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -1437,11 +1437,11 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, size_t data_in_sz) { int prp_size = NVME_PRP_SIZE; - __le64 *prp_entry, *prp1_entry, *prp2_entry, *prp_entry_phys; - __le64 *prp_page, *prp_page_phys; + __le64 *prp_entry, *prp1_entry, *prp2_entry; + __le64 *prp_page; + dma_addr_t prp_entry_dma, prp_page_dma, dma_addr; u32 offset, entry_len; u32 page_mask_result, page_mask; - dma_addr_t paddr; size_t length; /* @@ -1465,7 +1465,7 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * contiguous memory. */ prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); - prp_page_phys = (__le64 *)mpt3sas_base_get_pcie_sgl_dma(ioc, smid); + prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); /* * Check if we are within 1 entry of a page boundary we don't @@ -1476,21 +1476,21 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, if (!page_mask_result) { /* Bump up to next page boundary. */ prp_page = (__le64 *)((u8 *)prp_page + prp_size); - prp_page_phys = (__le64 *)((u8 *)prp_page_phys + prp_size); + prp_page_dma = prp_page_dma + prp_size; } /* * Set PRP physical pointer, which initially points to the current PRP * DMA memory page. */ - prp_entry_phys = prp_page_phys; + prp_entry_dma = prp_page_dma; /* Get physical address and length of the data buffer. */ if (data_in_sz) { - paddr = data_in_dma; + dma_addr = data_in_dma; length = data_in_sz; } else { - paddr = data_out_dma; + dma_addr = data_out_dma; length = data_out_sz; } @@ -1500,8 +1500,7 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * Check if we need to put a list pointer here if we are at * page boundary - prp_size (8 bytes). */ - page_mask_result = - (uintptr_t)((u8 *)prp_entry_phys + prp_size) & page_mask; + page_mask_result = (prp_entry_dma + prp_size) & page_mask; if (!page_mask_result) { /* * This is the last entry in a PRP List, so we need to @@ -1515,13 +1514,13 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * contiguous, no need to get a new page - it's * just the next address. */ - prp_entry_phys++; - *prp_entry = cpu_to_le64((uintptr_t)prp_entry_phys); + prp_entry_dma++; + *prp_entry = cpu_to_le64(prp_entry_dma); prp_entry++; } /* Need to handle if entry will be part of a page. */ - offset = (u32)paddr & page_mask; + offset = dma_addr & page_mask; entry_len = ioc->page_size - offset; if (prp_entry == prp1_entry) { @@ -1529,7 +1528,7 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * Must fill in the first PRP pointer (PRP1) before * moving on. */ - *prp1_entry = cpu_to_le64((u64)paddr); + *prp1_entry = cpu_to_le64(dma_addr); /* * Now point to the second PRP entry within the @@ -1549,8 +1548,7 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * list will start at the beginning of the * contiguous buffer. */ - *prp2_entry = - cpu_to_le64((uintptr_t)prp_entry_phys); + *prp2_entry = cpu_to_le64(prp_entry_dma); /* * The next PRP Entry will be the start of the @@ -1562,7 +1560,7 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * After this, the PRP Entries are complete. * This command uses 2 PRP's and no PRP list. */ - *prp2_entry = cpu_to_le64((u64)paddr); + *prp2_entry = cpu_to_le64(dma_addr); } } else { /* @@ -1572,16 +1570,16 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * all remaining PRP entries in a PRP List, one per * each time through the loop. */ - *prp_entry = cpu_to_le64((u64)paddr); + *prp_entry = cpu_to_le64(dma_addr); prp_entry++; - prp_entry_phys++; + prp_entry_dma++; } /* * Bump the phys address of the command's data buffer by the * entry_len. */ - paddr += entry_len; + dma_addr += entry_len; /* Decrement length accounting for last partial page. */ if (entry_len > length) @@ -1610,11 +1608,10 @@ base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, Mpi25SCSIIORequest_t *mpi_request, u16 smid, int sge_count) { - int sge_len, offset, num_prp_in_chain = 0; + int sge_len, num_prp_in_chain = 0; Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; __le64 *curr_buff; - dma_addr_t msg_phys; - u64 sge_addr; + dma_addr_t msg_dma, sge_addr, offset; u32 page_mask, page_mask_result; struct scatterlist *sg_scmd; u32 first_prp_len; @@ -1661,9 +1658,9 @@ base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, * page (4k). */ curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); - msg_phys = (dma_addr_t)mpt3sas_base_get_pcie_sgl_dma(ioc, smid); + msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); - main_chain_element->Address = cpu_to_le64(msg_phys); + main_chain_element->Address = cpu_to_le64(msg_dma); main_chain_element->NextChainOffset = 0; main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | @@ -1675,7 +1672,7 @@ base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, sge_addr = sg_dma_address(sg_scmd); sge_len = sg_dma_len(sg_scmd); - offset = (u32)(sge_addr & page_mask); + offset = sge_addr & page_mask; first_prp_len = nvme_pg_size - offset; ptr_first_sgl->Address = cpu_to_le64(sge_addr); @@ -1693,7 +1690,7 @@ base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, } for (;;) { - offset = (u32)(sge_addr & page_mask); + offset = sge_addr & page_mask; /* Put PRP pointer due to page boundary*/ page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; @@ -1701,15 +1698,15 @@ base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, scmd_printk(KERN_NOTICE, scmd, "page boundary curr_buff: 0x%p\n", curr_buff); - msg_phys += 8; - *curr_buff = cpu_to_le64(msg_phys); + msg_dma += 8; + *curr_buff = cpu_to_le64(msg_dma); curr_buff++; num_prp_in_chain++; } *curr_buff = cpu_to_le64(sge_addr); curr_buff++; - msg_phys += 8; + msg_dma += 8; num_prp_in_chain++; sge_addr += nvme_pg_size; @@ -2755,11 +2752,10 @@ mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) * * Returns phys pointer to the address of the PCIe buffer. */ -void * +dma_addr_t mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) { - return (void *)(uintptr_t) - (ioc->scsi_lookup[smid - 1].pcie_sg_list.pcie_sgl_dma); + return ioc->scsi_lookup[smid - 1].pcie_sg_list.pcie_sgl_dma; } /** diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index 2d7d44281cb7..60f42ca3954f 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -1395,7 +1395,7 @@ void *mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid); __le32 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid); void *mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid); -void *mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid); +dma_addr_t mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, +u16 smid); void mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc);