From patchwork Mon Oct 12 15:20:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 7376181 Return-Path: X-Original-To: patchwork-linux-scsi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EFA3CBF90C for ; Mon, 12 Oct 2015 15:05:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AB50220734 for ; Mon, 12 Oct 2015 15:05:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 98F3720742 for ; Mon, 12 Oct 2015 15:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752077AbbJLPFh (ORCPT ); Mon, 12 Oct 2015 11:05:37 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:11758 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751616AbbJLPFf (ORCPT ); Mon, 12 Oct 2015 11:05:35 -0400 Received: from 172.24.1.51 (EHLO szxeml432-hub.china.huawei.com) ([172.24.1.51]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CUB61530; Mon, 12 Oct 2015 23:05:15 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml432-hub.china.huawei.com (10.82.67.209) with Microsoft SMTP Server id 14.3.235.1; Mon, 12 Oct 2015 23:05:05 +0800 From: John Garry To: CC: , , , , , , , , , John Garry Subject: [PATCH 24/25] scsi: hisi_sas: add fatal irq handler Date: Mon, 12 Oct 2015 23:20:36 +0800 Message-ID: <1444663237-238302-25-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444663237-238302-1-git-send-email-john.garry@huawei.com> References: <1444663237-238302-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add handlers for fatal interrupts. Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 118 +++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c index b5ba46a..bc8e23e 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c @@ -1621,6 +1621,91 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) return IRQ_HANDLED; } +static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) +{ + struct hisi_hba *hisi_hba = p; + u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); + + if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { + u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); + + panic("Fatal DQ 1b ECC interrupt on controller %d (0x%x)\n", + hisi_hba->id, ecc_err); + } + + if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) { + u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) & + HGC_DQ_ECC_ADDR_BAD_MSK) >> + HGC_DQ_ECC_ADDR_BAD_OFF; + + panic("Fatal DQ RAM ECC interrupt on controller %d @ 0x%08x\n", + hisi_hba->id, addr); + } + + if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) { + u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); + + panic("Fatal IOST 1b ECC interrupt on controller %d (0x%x)\n", + hisi_hba->id, ecc_err); + } + + if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) { + u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) & + HGC_IOST_ECC_ADDR_BAD_MSK) >> + HGC_IOST_ECC_ADDR_BAD_OFF; + + panic("Fatal IOST RAM ECC interrupt on controller %d @ 0x%08x\n", + hisi_hba->id, addr); + } + + if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) { + u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) & + HGC_ITCT_ECC_ADDR_BAD_MSK) >> + HGC_ITCT_ECC_ADDR_BAD_OFF; + + panic("Fatal TCT RAM ECC interrupt on controller %d @ 0x%08x\n", + hisi_hba->id, addr); + } + + if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) { + u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); + + panic("Fatal ITCT 1b ECC interrupt on controller %d (0x%x)\n", + hisi_hba->id, ecc_err); + } + + hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f); + + return IRQ_HANDLED; +} + +static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) +{ + struct hisi_hba *hisi_hba = p; + u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); + u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); + + if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK) + panic("Fatal DQ_CFG_ERR interrupt on controller %d (0x%x)\n", + hisi_hba->id, axi_info); + + if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK) + panic("Fatal CQ_CFG_ERR interrupt on controller %d (0x%x)\n", + hisi_hba->id, axi_info); + + if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK) + panic("Fatal AXI_WRONG_INT interrupt on controller %d (0x%x)\n", + hisi_hba->id, axi_info); + + if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK) + panic("Fatal AXI_OVERLF_INT incorrect interrupt on controller %d (0x%x)\n", + hisi_hba->id, axi_info); + + hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000); + + return IRQ_HANDLED; +} + static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = { {"Bcast"}, {"Phy Up"}, @@ -1628,6 +1713,10 @@ static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = { }; static const char cq_int_name[32] = "cq"; +static const char fatal_int_name[HISI_SAS_FATAL_INT_NR][32] = { + "fatal ecc", + "fatal axi" +}; static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { int_bcast_v1_hw, @@ -1635,6 +1724,11 @@ static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { int_abnormal_v1_hw }; +static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = { + fatal_ecc_int_v1_hw, + fatal_axi_int_v1_hw +}; + int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) { int i, j, irq, rc, id = hisi_hba->id; @@ -1697,6 +1791,30 @@ int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) idx++; } + for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++) { + int idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + + hisi_hba->queue_count + i; + + irq = irq_of_parse_and_map(np, idx); + if (!irq) { + dev_err(dev, "irq init: [%d] could not map fatal interrupt %d\n", + hisi_hba->id, idx); + return -ENOENT; + } + (void)snprintf(&int_names[idx * HISI_SAS_NAME_LEN], + HISI_SAS_NAME_LEN, + DRV_NAME" %s [%d]", fatal_int_name[i], id); + rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0, + &int_names[idx * HISI_SAS_NAME_LEN], + hisi_hba); + if (rc) { + dev_err(dev, + "irq init: [%d] could not request fatal interrupt %d, rc=%d\n", + hisi_hba->id, irq, rc); + return -ENOENT; + } + idx++; + } return 0; }