From patchwork Thu Apr 5 15:46:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaitra P B X-Patchwork-Id: 10324831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 386B6600CB for ; Thu, 5 Apr 2018 15:47:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28A5A292CA for ; Thu, 5 Apr 2018 15:47:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1D444292CC; Thu, 5 Apr 2018 15:47:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7198F292CA for ; Thu, 5 Apr 2018 15:47:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751460AbeDEPrU (ORCPT ); Thu, 5 Apr 2018 11:47:20 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:38758 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750835AbeDEPrU (ORCPT ); Thu, 5 Apr 2018 11:47:20 -0400 Received: by mail-wm0-f66.google.com with SMTP id i3so8427672wmf.3 for ; Thu, 05 Apr 2018 08:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RprNQLuphtOGwFJWc93YsHg+pHGhXl6OXY4oYV5sTKM=; b=XA6Iofaio4GU2dQqyJQpuJHcRimkAVz8P/L9v/puErwqSyunhh4iWXGo6EHlsUmdbL 5TQJ2dlx5ouzahgH5aDDiWjCdi4YbRJQwbRqygAALy9o0+5GQTm87qXbGnWTvG7urgoT Hg+PS80RpMwiMyBYZOv0GStU30WDXob7qdq8A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RprNQLuphtOGwFJWc93YsHg+pHGhXl6OXY4oYV5sTKM=; b=foayzzpBN9esdq+XEjgCUz1Dx8N7Bey91w8gPcuZOrmF5cBhuxLkt5B3M8CD+Uk9PV +XUgPts4xLCNZt0nA8lEbREEzj4uy+FA0+dQnQEEE4oGv1Pf3GtP1lRtXWRL73Apf6Yj w85VoNnmU0QGNoHGjXmmnhVBFE0dsSb8gi+V6ZdP+I5Of3bjufoNo6KuHP3hkYK7aP4e fU5luXiR6tw6i1URlPdyI8+VBECFaO9NLje5URpfOVcVUWJ7ToHPDn/GdncngUuVOat2 8vtQV6RFZBS5Hi21Ux9keTcr48zJVDqojVzp/aBP8E+2NyLgZ+yfr9Zif7bs+RzfC21I 9uGQ== X-Gm-Message-State: ALQs6tD9H3FwanItrCcwNYquLegB9ejs4VTvRPqYLYrNBWkc918HRMUS RKMguWIQFMjXj/PhiWQ0VW2u70A9 X-Google-Smtp-Source: AIpwx4+KaTa9U/x5TAwoaZrrXRIBMaiYzPbGYIJAvLnGYoNKtMjZpzzxlvN40868GJCaIu+VBodeEg== X-Received: by 10.80.172.196 with SMTP id x62mr3427566edc.265.1522943238779; Thu, 05 Apr 2018 08:47:18 -0700 (PDT) Received: from localhost.localdomain.localdomain ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id p91sm4745777edp.65.2018.04.05.08.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Apr 2018 08:47:18 -0700 (PDT) From: Chaitra P B To: linux-scsi@vger.kernel.org Cc: Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, suganath-prabu.subramani@broadcom.com, Chaitra P B Subject: [PATCH v1 05/15] mpt3sas: Optimize I/O memory consumption in driver. Date: Thu, 5 Apr 2018 11:46:27 -0400 Message-Id: <1522943197-5408-6-git-send-email-chaitra.basappa@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1522943197-5408-1-git-send-email-chaitra.basappa@broadcom.com> References: <1522943197-5408-1-git-send-email-chaitra.basappa@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For every IO, memory of PAGE size is allocated for handling NVMe native PRPS. And in addition to that for every IO (chains need per IO * chain buffer size, e.g. 38 * 128byte) amount of memory is allocated for chain buffers. However, at any point of time; the IO request can be for NVMe target device (where PRP's page is used for framing PRP's) or can be for SCSI target device (where chain buffers are used for framing chain SGE's). This patch modifies the driver to reuse same pre-allocated PRP page buffers as a chain buffer for IO's targeted for SCSI target devices. No need to allocate separate buffers for chain SGE's buffers. Suppose if the number of chain buffers need for IO doesn't fit in the PRP Page size then driver maintain's separate buffers for those extra chain buffers that exceeds the PRP page size. For example consider PRP page size as 4K and chain buffer size as 128 bytes, then number of chain buffers that can fit in PRP page is 4096/128 => 32. if the number of chain buffer need per IO exceeds 32; for example consider number of chains need per IO is 36 then for remaining 4 chain buffer's driver allocates them individual. Signed-off-by: Chaitra P B Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 80 +++++++++++++++++++++++-------------- 1 file changed, 51 insertions(+), 29 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 1e8e399..701e1e7 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4188,7 +4188,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) kfree(ioc->internal_lookup); if (ioc->chain_lookup) { for (i = 0; i < ioc->scsiio_depth; i++) { - for (j = 0; j < ioc->chains_needed_per_io; j++) { + for (j = ioc->chains_per_prp_buffer; + j < ioc->chains_needed_per_io; j++) { ct = &ioc->chain_lookup[i].chains_per_smid[j]; if (ct && ct->chain_buffer) dma_pool_free(ioc->chain_dma_pool, @@ -4506,7 +4507,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); if (!ioc->chain_lookup) { pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages " - "failed\n", ioc->name); + "failed\n", ioc->name); goto out; } @@ -4520,33 +4521,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) } } - ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, - ioc->chain_segment_sz, 16, 0); - if (!ioc->chain_dma_pool) { - pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", - ioc->name); - goto out; - } - for (i = 0; i < ioc->scsiio_depth; i++) { - for (j = 0; j < ioc->chains_needed_per_io; j++) { - ct = &ioc->chain_lookup[i].chains_per_smid[j]; - ct->chain_buffer = dma_pool_alloc( - ioc->chain_dma_pool , GFP_KERNEL, - &ct->chain_buffer_dma); - if (!ct->chain_buffer) { - pr_err(MPT3SAS_FMT "chain_lookup: " - " pci_pool_alloc failed\n", ioc->name); - goto out; - } - } - total_sz += ioc->chain_segment_sz; - } - - dinitprintk(ioc, pr_info(MPT3SAS_FMT - "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", - ioc->name, ioc->chain_depth, ioc->chain_segment_sz, - ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); - /* initialize hi-priority queue smid's */ ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, sizeof(struct request_tracker), GFP_KERNEL); @@ -4587,6 +4561,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) * be required for NVMe PRP's, only each set of NVMe blocks will be * contiguous, so a new set is allocated for each possible I/O. */ + ioc->chains_per_prp_buffer = 0; if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { nvme_blocks_needed = (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; @@ -4609,6 +4584,11 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->name); goto out; } + + ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; + ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer, + ioc->chains_needed_per_io); + for (i = 0; i < ioc->scsiio_depth; i++) { ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc( ioc->pcie_sgl_dma_pool, GFP_KERNEL, @@ -4619,13 +4599,55 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->name); goto out; } + for (j = 0; j < ioc->chains_per_prp_buffer; j++) { + ct = &ioc->chain_lookup[i].chains_per_smid[j]; + ct->chain_buffer = + ioc->pcie_sg_lookup[i].pcie_sgl + + (j * ioc->chain_segment_sz); + ct->chain_buffer_dma = + ioc->pcie_sg_lookup[i].pcie_sgl_dma + + (j * ioc->chain_segment_sz); + } } dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), " "element_size(%d), pool_size(%d kB)\n", ioc->name, ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); + dinitprintk(ioc, pr_info(MPT3SAS_FMT "Number of chains can " + "fit in a PRP page(%d)\n", ioc->name, + ioc->chains_per_prp_buffer)); total_sz += sz * ioc->scsiio_depth; } + + ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, + ioc->chain_segment_sz, 16, 0); + if (!ioc->chain_dma_pool) { + pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", + ioc->name); + goto out; + } + for (i = 0; i < ioc->scsiio_depth; i++) { + for (j = ioc->chains_per_prp_buffer; + j < ioc->chains_needed_per_io; j++) { + ct = &ioc->chain_lookup[i].chains_per_smid[j]; + ct->chain_buffer = dma_pool_alloc( + ioc->chain_dma_pool, GFP_KERNEL, + &ct->chain_buffer_dma); + if (!ct->chain_buffer) { + pr_err(MPT3SAS_FMT "chain_lookup: " + " pci_pool_alloc failed\n", ioc->name); + _base_release_memory_pools(ioc); + goto out; + } + } + total_sz += ioc->chain_segment_sz; + } + + dinitprintk(ioc, pr_info(MPT3SAS_FMT + "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", + ioc->name, ioc->chain_depth, ioc->chain_segment_sz, + ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); + /* sense buffers, 4 byte align */ sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,