From patchwork Thu Feb 21 09:50:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 10823423 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B75791390 for ; Thu, 21 Feb 2019 09:50:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A5F2E2FB62 for ; Thu, 21 Feb 2019 09:50:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A3FDB301E5; Thu, 21 Feb 2019 09:50:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E5D12FF04 for ; Thu, 21 Feb 2019 09:50:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727148AbfBUJuz (ORCPT ); Thu, 21 Feb 2019 04:50:55 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:2138 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725823AbfBUJuz (ORCPT ); Thu, 21 Feb 2019 04:50:55 -0500 X-UUID: 390a57afeee5431f88b44921b5300649-20190221 X-UUID: 390a57afeee5431f88b44921b5300649-20190221 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 858934022; Thu, 21 Feb 2019 17:50:46 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 17:50:45 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 17:50:45 +0800 From: To: , , , CC: , , , , , , , Stanley Chu Subject: [PATCH v1 1/2] dt-bindings: scsi: ufs: Add document for ufs-mediatek Date: Thu, 21 Feb 2019 17:50:36 +0800 Message-ID: <1550742637-12385-3-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1550742637-12385-1-git-send-email-stanley.chu@mediatek.com> References: <1550742637-12385-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stanley Chu Add UFS and UFS PHY node document for Mediatek SoC chips. Signed-off-by: Stanley Chu --- .../devicetree/bindings/ufs/ufs-mediatek.txt | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt new file mode 100644 index 000000000000..c09a4f884bea --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt @@ -0,0 +1,62 @@ +* Mediatek Universal Flash Storage (UFS) Host Controller + +UFS nodes are defined to describe on-chip UFS hardware macro. +Each UFS Host Controller should have its own node. + +UFS PHY nodes are defined to describe on-chip UFS PHY hardware macro. +Each UFS PHY node should have its own node. + +Required properties for UFS nodes: +- compatible : Compatible list, contains the following controller: + "mediatek,ufshci" +- reg : Address and length of the UFS register set. +- interrupt-parent : interrupt device. +- interrupts : interrupt number. +- clocks : List of phandle and clock specifier pairs. +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. "ufs0-clock", "ufs0-unipro-clk" and + "ufs0-mp-clk" are mandatory. +- freq-table-hz : Array of operating frequencies stored in the same + order as the clocks property. If this property is not + defined or a value in the array is "0" then it is assumed + that the frequency is set by the parent clock or a + fixed rate clock source. +- vcc-supply : Power to the UFS device. +- vcc-fixed-regulator: Specify that vcc-supply is a fixed regulator. +- lanes-per-direction: Number of lanes available per direction. Shall be 1. + +Required properties for UFS PHY nodes: +- compatible : Compatible list, contains the following controller: + "mediatek,ufs_mphy" +- reg : Address and length of the UFS PHY register set. + +Example: + + ufshci:ufshci@11270000 { + compatible = "mediatek,ufshci"; + reg = <0 0x11270000 0 0x2300>; + interrupts = ; + + clocks = + <&infracfg_ao INFRACFG_AO_UFS_CG>, + <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>, + <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>; + clock-names = + "ufs0-clock", + "ufs0-unipro-clk", + "ufs0-mp-clk"; + freq-table-hz = + <0 0>, + <0 0>, + <0 0>; + + vcc-supply = <&mt_pmic_vemc_ldo_reg>; + vcc-fixed-regulator; + + lanes-per-direction = <1>; + }; + + ufs_mphy@11fa0000 { + compatible = "mediatek,ufs_mphy"; + reg = <0 0x11fa0000 0 0xc000>; + };