From patchwork Fri Jun 16 06:51:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: butao X-Patchwork-Id: 9790637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A6DCB60326 for ; Fri, 16 Jun 2017 06:53:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9EF8F27E63 for ; Fri, 16 Jun 2017 06:53:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 93B0D28547; Fri, 16 Jun 2017 06:53:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 51C4727E63 for ; Fri, 16 Jun 2017 06:53:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752387AbdFPGvq (ORCPT ); Fri, 16 Jun 2017 02:51:46 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:7431 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752077AbdFPGvp (ORCPT ); Fri, 16 Jun 2017 02:51:45 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APM20843; Fri, 16 Jun 2017 14:51:34 +0800 (CST) Received: from vm107-72-191.huawei.com (100.107.72.191) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Fri, 16 Jun 2017 14:51:23 +0800 From: Bu Tao To: , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v2 3/5] arm64: dts: Add ufs dts node Date: Fri, 16 Jun 2017 14:51:17 +0800 Message-ID: <20170616065119.10704-4-butao@hisilicon.com> X-Mailer: git-send-email 2.11.GIT In-Reply-To: <20170616065119.10704-1-butao@hisilicon.com> References: <20170616065119.10704-1-butao@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [100.107.72.191] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0204.59437FF6.00B2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2646b3a774610cdb8a8baf02c620c51d Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP arm64: dts: add ufs node for hi3660 Signed-off-by: Bu Tao --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 9 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 19 +++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 186251ffc6b2..5dbe642f3c66 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -32,3 +32,12 @@ &uart5 { status = "okay"; }; + +&ufs { + ufs-hi3660-use-rate-B; + ufs-hi3660-broken-fastauto; + ufs-hi3660-use-HS-GEAR3; + ufs-hi3660-broken-clk-gate-bypass; + reset-gpio = <&gpio18 1 0>; + status = "okay"; +} diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086bd67b..e688fdb0a939 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -141,6 +141,25 @@ #size-cells = <2>; ranges; + ufs: ufs@ff3b0000 { + compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3b0000 0x0 0x1000>, + <0x0 0xff3b1000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; + clock-names = "clk_ref", "clk_phy"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + /* offset: 0x84; bit: 7 */ + resets = <&crg_rst 0x84 12>, + <&crg_rst 0x84 7>; + reset-names = "rst", "assert"; + }; + fixed_uart5: fixed_19_2M { compatible = "fixed-clock"; #clock-cells = <0>;