From patchwork Wed Jan 29 07:39:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11355601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02D57112B for ; Wed, 29 Jan 2020 07:39:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CAB8320708 for ; Wed, 29 Jan 2020 07:39:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SCBPwcpc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726317AbgA2HjS (ORCPT ); Wed, 29 Jan 2020 02:39:18 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:15399 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726245AbgA2HjP (ORCPT ); Wed, 29 Jan 2020 02:39:15 -0500 X-UUID: 10b6da7c35194dc5835daaa543df793e-20200129 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ihJg6nDDfiwxmrOIMOxnedl2OexPLbIqUMUcg8QFLQA=; b=SCBPwcpcolSaFPCrFKTMHaZ7FCb3H6BfW2x1QLm2jwZrEvbQpnlb8zmQgwbVelZSqA2QZE/5kMVdWdFsOV4/Y2jNGHW9nIk+viZ8l/nVevhRvMOx1w1d5wdC4B5PdUztwhs/itRbg2JOu5QTK/pYCbYnu+fDo0RZ7A5VnX/NpnY=; X-UUID: 10b6da7c35194dc5835daaa543df793e-20200129 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1642458441; Wed, 29 Jan 2020 15:39:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 29 Jan 2020 15:37:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 29 Jan 2020 15:39:12 +0800 From: Stanley Chu To: , , , , , CC: , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 4/4] scsi: ufs-mediatek: gate ref-clk during Auto-Hibern8 Date: Wed, 29 Jan 2020 15:39:02 +0800 Message-ID: <20200129073902.5786-5-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200129073902.5786-1-stanley.chu@mediatek.com> References: <20200129073902.5786-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 93F3D5635F3DD161DD5DA950D7204A42ABF40BAE1E4F29319C737A0899891C622000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org In current UFS driver design, hba->uic_link_state will not be changed after link enters Hibern8 state by Auto-Hibern8 mechanism. In this case, reference clock gating will be skipped unless special handling is implemented in vendor's callbacks. Support reference clock gating during Auto-Hibern8 period in MediaTek Chipsets: If link state is already in Hibern8 while Auto-Hibern8 feature is enabled, gate reference clock in setup_clocks callback. Signed-off-by: Stanley Chu Reviewed-by: Alim Akhtar --- drivers/scsi/ufs/ufs-mediatek.c | 38 +++++++++++++++++++++++---------- drivers/scsi/ufs/ufs-mediatek.h | 12 +++++++++++ 2 files changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index d78897a14905..0ce08872d671 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -143,6 +143,17 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) return 0; } +static u32 ufs_mtk_link_get_state(struct ufs_hba *hba) +{ + u32 val; + + ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); + val = ufshcd_readl(hba, REG_UFS_PROBE); + val = val >> 28; + + return val; +} + /** * ufs_mtk_setup_clocks - enables/disable clocks * @hba: host controller instance @@ -155,7 +166,7 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, enum ufs_notify_change_status status) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); - int ret = -EINVAL; + int ret = 0; /* * In case ufs_mtk_init() is not yet done, simply ignore. @@ -165,19 +176,24 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, if (!host) return 0; - switch (status) { - case PRE_CHANGE: - if (!on && !ufshcd_is_link_active(hba)) { + if (!on && status == PRE_CHANGE) { + if (!ufshcd_is_link_active(hba)) { ufs_mtk_setup_ref_clk(hba, on); ret = phy_power_off(host->mphy); + } else { + /* + * Gate ref-clk if link state is in Hibern8 + * triggered by Auto-Hibern8. + */ + if (!ufshcd_can_hibern8_during_gating(hba) && + ufshcd_is_auto_hibern8_enabled(hba) && + ufs_mtk_link_get_state(hba) == + VS_LINK_HIBERN8) + ufs_mtk_setup_ref_clk(hba, on); } - break; - case POST_CHANGE: - if (on) { - ret = phy_power_on(host->mphy); - ufs_mtk_setup_ref_clk(hba, on); - } - break; + } else if (on && status == POST_CHANGE) { + ret = phy_power_on(host->mphy); + ufs_mtk_setup_ref_clk(hba, on); } return ret; diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index fccdd979d6fb..492414e5f481 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -53,6 +53,18 @@ #define VS_SAVEPOWERCONTROL 0xD0A6 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 +/* + * Vendor specific link state + */ +enum { + VS_LINK_DISABLED = 0, + VS_LINK_DOWN = 1, + VS_LINK_UP = 2, + VS_LINK_HIBERN8 = 3, + VS_LINK_LOST = 4, + VS_LINK_CFG = 5, +}; + /* * SiP commands */