From patchwork Fri May 29 09:23:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11578197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04EF8912 for ; Fri, 29 May 2020 09:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF511207F5 for ; Fri, 29 May 2020 09:23:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GQgGtA2y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726774AbgE2JXV (ORCPT ); Fri, 29 May 2020 05:23:21 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:37427 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726644AbgE2JXS (ORCPT ); Fri, 29 May 2020 05:23:18 -0400 X-UUID: bb431eba164c4b839de1b208f8d91198-20200529 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=NOKlv7zM4LRTruut6jgdhOjKQWFJHmbjuA06RuI5wcQ=; b=GQgGtA2y+2a6srv8ldiq1g47YvQxUB5fqMKbjAE7fE7jc9Z0A920YW63wNAiBq7cCJQzGepW/zyhJbtxkTSsv8m5AIXVBa7mPrrbfENcr+XFVx28dNov42ThCTdi16+lo+cXr6V9XKbqZx5nh9euHX0i8iLYMZ7OnhaLiXzyZDQ=; X-UUID: bb431eba164c4b839de1b208f8d91198-20200529 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 47945482; Fri, 29 May 2020 17:23:14 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 29 May 2020 17:23:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 29 May 2020 17:23:10 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , , , , Stanley Chu Subject: [PATCH v2 4/5] scsi: ufs-mediatek: Fix unbalanced clock on/off Date: Fri, 29 May 2020 17:23:09 +0800 Message-ID: <20200529092310.1106-5-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200529092310.1106-1-stanley.chu@mediatek.com> References: <20200529092310.1106-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 83DAA400323415FEC60197EA0FAEFFA75DFAD431B49159932AD28C3CD9C819842000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org MediaTek UFS clocks are separated to two parts and controlled by different modules: ufs-mediatek and phy-ufs-mediatek. If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control is not balanced thus unbalanced control also happens to the clocks probed by phy-ufs-mediatek module. Fix this issue by - Promise usage of phy_power_on/off balanced - Remove phy_power_on/off control in suspend/resume vops since both can be handled in setup_clock vops only Signed-off-by: Stanley Chu Reviewed-by: Peter Wang --- drivers/scsi/ufs/ufs-mediatek.c | 56 +++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 5f41b7b7db8f..de9e643fb8dd 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -205,6 +205,23 @@ int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, return -ETIMEDOUT; } +static void ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + struct phy *mphy = host->mphy; + + if (!mphy) + return; + + if (on && !host->mphy_powered_on) + phy_power_on(mphy); + else if (!on && host->mphy_powered_on) + phy_power_off(mphy); + else + return; + host->mphy_powered_on = on; +} + /** * ufs_mtk_setup_clocks - enables/disable clocks * @hba: host controller instance @@ -228,25 +245,24 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, return 0; if (!on && status == PRE_CHANGE) { - if (!ufshcd_is_link_active(hba)) { - ufs_mtk_setup_ref_clk(hba, on); - ret = phy_power_off(host->mphy); - } else { - /* - * Gate ref-clk if link state is in Hibern8 - * triggered by Auto-Hibern8. - */ - if (!ufshcd_can_hibern8_during_gating(hba) && - ufshcd_is_auto_hibern8_enabled(hba)) { - ret = ufs_mtk_wait_link_state(hba, - VS_LINK_HIBERN8, - 15); - if (!ret) - ufs_mtk_setup_ref_clk(hba, on); + /* + * Gate ref-clk and poweroff mphy if link state is in OFF + * or Hibern8 by either ufshcd_link_state_transition() or + * Auto-Hibern8. + */ + if (!ufshcd_is_link_active(hba) || + (!ufshcd_can_hibern8_during_gating(hba) && + ufshcd_is_auto_hibern8_enabled(hba))) { + ret = ufs_mtk_wait_link_state(hba, + VS_LINK_HIBERN8, + 15); + if (!ret) { + ufs_mtk_setup_ref_clk(hba, on); + ufs_mtk_mphy_power_on(hba, on); } } } else if (on && status == POST_CHANGE) { - ret = phy_power_on(host->mphy); + ufs_mtk_mphy_power_on(hba, on); ufs_mtk_setup_ref_clk(hba, on); } @@ -538,7 +554,6 @@ static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { int err; - struct ufs_mtk_host *host = ufshcd_get_variant(hba); if (ufshcd_is_link_hibern8(hba)) { err = ufs_mtk_link_set_lpm(hba); @@ -559,20 +574,13 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) ufs_mtk_vreg_set_lpm(hba, true); } - if (!ufshcd_is_link_active(hba)) - phy_power_off(host->mphy); - return 0; } static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { - struct ufs_mtk_host *host = ufshcd_get_variant(hba); int err; - if (!ufshcd_is_link_active(hba)) - phy_power_on(host->mphy); - if (ufshcd_is_link_hibern8(hba)) { ufs_mtk_vreg_set_lpm(hba, false); err = ufs_mtk_link_set_hpm(hba);