From patchwork Wed Aug 19 08:43:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11723273 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32EE8618 for ; Wed, 19 Aug 2020 08:43:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 194E9207DE for ; Wed, 19 Aug 2020 08:43:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sq2coitV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726664AbgHSInq (ORCPT ); Wed, 19 Aug 2020 04:43:46 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:17227 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725903AbgHSInp (ORCPT ); Wed, 19 Aug 2020 04:43:45 -0400 X-UUID: 833d184e013544a493d81f99e5afc5a3-20200819 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=AECUkhYUHBHHNyZQuHsduJ7+PYMR4h3yA3w0YXFQIAA=; b=sq2coitVuMZkfuGBl2AkCsuFUClEws7szVGl4t20fw/WQnAPvH5I0ahgpRzzbAwB+1vo60ayt/D3J02vMd5saLV7IyebFm6LB7y4Ea3YOp18Ks7zQQGvvJuiTSnBMM34tmf07fcpWnBwOO/Ih4Eoi5YUODcZV8p6LeY9XLDKVwg=; X-UUID: 833d184e013544a493d81f99e5afc5a3-20200819 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 975283013; Wed, 19 Aug 2020 16:43:42 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 19 Aug 2020 16:43:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 19 Aug 2020 16:43:39 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , Stanley Chu Subject: [PATCH] scsi: ufs-mediatek: Modify the minimum RX/TX lane count to 2 Date: Wed, 19 Aug 2020 16:43:40 +0800 Message-ID: <20200819084340.7021-1-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Andy Teng MediaTek UFS host starts to support 2 lanes, thus modify the minimum lane count to 2. This modification shall not impact old 1-lane host because PA_CONNECTEDRXDATALANES and PA_CONNECTEDTXDATALANES will limit the target lanes properly during power mode change. So we could relax the limitation in ufs_dev_params. Reviewed-by: Stanley Chu Signed-off-by: Andy Teng Singed-off-by: Stanley Chu Reviewed-by: Avri Altman --- drivers/scsi/ufs/ufs-mediatek.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index 8ed24d5fcff9..87657376d27a 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -33,8 +33,8 @@ /* * Vendor specific pre-defined parameters */ -#define UFS_MTK_LIMIT_NUM_LANES_RX 1 -#define UFS_MTK_LIMIT_NUM_LANES_TX 1 +#define UFS_MTK_LIMIT_NUM_LANES_RX 2 +#define UFS_MTK_LIMIT_NUM_LANES_TX 2 #define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3 #define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3 #define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4