diff mbox series

[2/7] ufs: add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS

Message ID 20220412073647.3808493-3-yoshihiro.shimoda.uh@renesas.com (mailing list archive)
State Superseded
Headers show
Series treewide: scsi: ufs: Add support for Renesas R-Car UFS controller | expand

Commit Message

Yoshihiro Shimoda April 12, 2022, 7:36 a.m. UTC
Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS for a broken host controller
of the 64-bit addressing supported capability.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/scsi/ufs/ufshcd.c | 3 ++-
 drivers/scsi/ufs/ufshcd.h | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

Comments

Christoph Hellwig April 15, 2022, 6:45 a.m. UTC | #1
On Tue, Apr 12, 2022 at 04:36:42PM +0900, Yoshihiro Shimoda wrote:
> Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS for a broken host controller
> of the 64-bit addressing supported capability.

Why can't you just clear MASK_64_ADDRESSING_SUPPORT for this case?
Yoshihiro Shimoda April 15, 2022, 7:45 a.m. UTC | #2
Hi Christoph,

> From: Christoph Hellwig, Sent: Friday, April 15, 2022 3:46 PM
> 
> On Tue, Apr 12, 2022 at 04:36:42PM +0900, Yoshihiro Shimoda wrote:
> > Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS for a broken host controller
> > of the 64-bit addressing supported capability.
> 
> Why can't you just clear MASK_64_ADDRESSING_SUPPORT for this case?

Unfortunately, the register (REG_CONTROLLER_CAPABILITIES) is read-only.
So, software cannot clear MASK_64_ADDRESSING_SUPPORT on the register.
I am also asking a person in charge of hardware why the MASK_64_ADDRESSING_SUPPORT
is set now, but I didn't get any feedback yet...

However, we can add the following code instead. Perhaps, it's better than the current patch?

---
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2201,6 +2201,9 @@ static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
 	((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
 	hba->reserved_slot = hba->nutrs - 1;
 
+	if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
+		hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
+
 	/* Read crypto capabilities */
 	err = ufshcd_hba_init_crypto_capabilities(hba);
 	if (err)
---

Best regards,
Yoshihiro Shimoda
diff mbox series

Patch

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3f9caafa91bf..a7bb3945c7c6 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -9513,7 +9513,8 @@  EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
  */
 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
 {
-	if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
+	if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) &&
+	    hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
 		if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
 			return 0;
 	}
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 94f545be183a..1745144eb904 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -602,6 +602,12 @@  enum ufshcd_quirks {
 	 * support physical host configuration.
 	 */
 	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
+
+	/*
+	 * This quirk needs to be enabled if the host controller has
+	 * 64-bit addressing supported capability but it doesn't work.
+	 */
+	UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		= 1 << 17,
 };
 
 enum ufshcd_caps {