From patchwork Thu Aug 25 07:54:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sreekanth Reddy X-Patchwork-Id: 12954308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBF9DC28D13 for ; Thu, 25 Aug 2022 07:42:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238511AbiHYHmv (ORCPT ); Thu, 25 Aug 2022 03:42:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238468AbiHYHmo (ORCPT ); Thu, 25 Aug 2022 03:42:44 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F9279DB4C for ; Thu, 25 Aug 2022 00:42:43 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id bh13so17180746pgb.4 for ; Thu, 25 Aug 2022 00:42:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc; bh=h9s46oAmPCQL0s1h3/VJrjMdopyqM1mwca5/TWZPItw=; b=VXhwnLvgpPB7jqfjwxjBI7yjSuPVJPqf5pNjaNlNAlyfbzgDNvVfTht1H74vktDPwO FzNidJuUEei3U7fkX9yU1ish9XuJ/koIodoucanq7rGLBZpfI5iPRfzWEZ6KaDUwF7UO oosLcGAi3uieWm/TgDL1ermPsB5nMFk3yMLWc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc; bh=h9s46oAmPCQL0s1h3/VJrjMdopyqM1mwca5/TWZPItw=; b=Q3YQoprb9o+rxM4pZCPO8BomYlKzRAlUqmrWrW9GRuwVXSHeZeOKTA+ikfQlsHDLjP AG4gruNiXLyPhnp8EBDv9a+RcGvVgnItttQdcDKoY611x/4cbvJPRpWz/bhe5N1wajB0 OhyT06faCUY4oV+r6/D3YXchhyMOnvF24Wi4du0fMnl3DayKi3b24dj5wwDBR3s0EYoA T0bENvKMYlqgw+2QGgSkGLuAVeiq3XCrUagiH5wpaWnl697kU3IxWrnPU0GjDBqx6eF3 +xq0FY6/uMQenwbZYg4QiR6aCkpqpJ0mvi8CNK+ClqdGAagyqZJ6tymYK1n1qfWtkySR LBPQ== X-Gm-Message-State: ACgBeo3S5yNOgJ4Urdpi76jhDKmMMc4I0aFTN5hrckbCxS9Ms3TCzU5M PcfNJlD7jjA32ZrZP4sdqlHVlzmzlUm9akXoj/irdFHN8pOhWfm43mrR6lTFSXHslDMbuhrI2SA jblzWkMnTGXxLZ4G1pubzt++eiZpDWho0q7DDeXD5tzCZWKyIDde1v2S5zxjMbwxwdcImWuiwNF IGeJvpar0w X-Google-Smtp-Source: AA6agR7V2155Ow0bsQZucfkwEWyMSUMYSUbnlqI9ouYjfltV7lOjaQyH39Z4eFdzAciY5D9+2/G15Q== X-Received: by 2002:a05:6a00:21c2:b0:52b:ff44:6680 with SMTP id t2-20020a056a0021c200b0052bff446680mr2659418pfj.57.1661413361979; Thu, 25 Aug 2022 00:42:41 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id ns3-20020a17090b250300b001fbb0d07363sm644916pjb.39.2022.08.25.00.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 00:42:41 -0700 (PDT) From: Sreekanth Reddy To: linux-scsi@vger.kernel.org Cc: martin.petersen@oracle.com, Sreekanth Reddy Subject: [PATCH v2 1/4] mpt3sas: Don't change dma mask while reallocating pools Date: Thu, 25 Aug 2022 13:24:54 +0530 Message-Id: <20220825075457.16422-2-sreekanth.reddy@broadcom.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220825075457.16422-1-sreekanth.reddy@broadcom.com> References: <20220825075457.16422-1-sreekanth.reddy@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org When a pool crosses the 4gb boundary region then before reallocation pools just change the coherent dma mask to 32bit and keep the normal dma mask to 63/64 bit. Signed-off-by: Sreekanth Reddy --- drivers/scsi/mpt3sas/mpt3sas_base.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index eeebe80..f8a3b0d 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2990,19 +2990,26 @@ static int _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) { struct sysinfo s; + u64 coherent_dma_mask, dma_mask; - if (ioc->is_mcpu_endpoint || - sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma || - dma_get_required_mask(&pdev->dev) <= 32) + if (ioc->is_mcpu_endpoint || sizeof(dma_addr_t) == 4 || + dma_get_required_mask(&pdev->dev) <= 32) { ioc->dma_mask = 32; + coherent_dma_mask = dma_mask = DMA_BIT_MASK(32); /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ - else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) + } else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) { ioc->dma_mask = 63; - else + coherent_dma_mask = dma_mask = DMA_BIT_MASK(63); + } else { ioc->dma_mask = 64; + coherent_dma_mask = dma_mask = DMA_BIT_MASK(64); + } + + if (ioc->use_32bit_dma) + coherent_dma_mask = DMA_BIT_MASK(32); - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) || - dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask))) + if (dma_set_mask(&pdev->dev, dma_mask) || + dma_set_coherent_mask(&pdev->dev, coherent_dma_mask)) return -ENODEV; if (ioc->dma_mask > 32) {