From patchwork Wed Feb 15 12:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Po-Wen Kao X-Patchwork-Id: 13141600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96E7EC636CC for ; Wed, 15 Feb 2023 12:38:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234066AbjBOMiU (ORCPT ); Wed, 15 Feb 2023 07:38:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234055AbjBOMiR (ORCPT ); Wed, 15 Feb 2023 07:38:17 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 247BF3802D; Wed, 15 Feb 2023 04:38:15 -0800 (PST) X-UUID: 9a517f7aad2d11eda06fc9ecc4dadd91-20230215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=f9EBWwssS/YFeyn8xKypBqeYW3Z1Yj/I0JqpK089PLs=; b=aMFe+e6jgv0jFr3pUAgzxN6I9U0SCTrcvPzyHILbn9Rx8IsQNDb9RHiisTW/XmcgSBNTBZYqnxyzFKNEfBJrH7EQuHy15dxb4lTUnQvzyiEJSGwdQn7zijunfQuAxsRsViFSu5keGW7c47YDHz0ScZ58Ku4wdTpu48nTi9MBYZo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:c1540f21-d421-4bcb-bce2-f9f9010e351f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:885ddb2,CLOUDID:fd5817f3-ddba-41c3-91d9-10eeade8eac7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: 9a517f7aad2d11eda06fc9ecc4dadd91-20230215 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 752279861; Wed, 15 Feb 2023 20:38:09 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 15 Feb 2023 20:38:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 15 Feb 2023 20:38:07 +0800 From: Po-Wen Kao To: Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger CC: , , , , , , , , , , , , , , Subject: [PATCH 2/2] scsi: ufs: core: Export symbol ufshcd_mcq_read_cqis() Date: Wed, 15 Feb 2023 20:37:46 +0800 Message-ID: <20230215123750.15785-2-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230215123750.15785-1-powen.kao@mediatek.com> References: <20230215123750.15785-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Export symbol for driver module Signed-off-by: Po-Wen Kao --- drivers/ufs/core/ufs-mcq.c | 1 + include/ufs/ufshcd.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 3a27fa4b0024..c97b45cd94ee 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -241,6 +241,7 @@ u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i) { return readl(mcq_opr_base(hba, OPR_CQIS, i) + REG_CQIS); } +EXPORT_SYMBOL_GPL(ufshcd_mcq_read_cqis); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i) { diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index ed9e3d5addb3..57e3b9524b1b 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1243,6 +1243,8 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); void ufshcd_hba_stop(struct ufs_hba *hba); void ufshcd_schedule_eh_work(struct ufs_hba *hba); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); +u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); + unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba *hba, struct ufs_hw_queue *hwq); void ufshcd_mcq_enable_esi(struct ufs_hba *hba);