| Message ID | 20230926162042.14180-3-quic_nitirawa@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add UFS host controller and Phy nodes for sc7280 | expand |
On 26.09.2023 18:20, Nitin Rawat wrote: > Add UFS host controller and PHY nodes for sc7280 soc. > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 66f1eb83cca7..3be8ea090ade 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -3353,6 +3353,70 @@ > }; > }; > > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", > + "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x80 0x0>; > + dma-coherent; > + > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; As discussed, property-names is preferred to come after property, just like in the other node you're adding. [...] > + ufs_mem_phy: phy@1d87000 { > + compatible = "qcom,sc7280-qmp-ufs-phy"; > + reg = <0x0 0x01d87000 0x0 0xe00>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_UFS_1_CLKREF_EN>; > + clock-names = "ref", "ref_aux", "qref"; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + > + }; Stray newline above. Konrad
On 9/27/2023 12:01 AM, Konrad Dybcio wrote: > On 26.09.2023 18:20, Nitin Rawat wrote: >> Add UFS host controller and PHY nodes for sc7280 soc. >> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++++++ >> 1 file changed, 64 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 66f1eb83cca7..3be8ea090ade 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -3353,6 +3353,70 @@ >> }; >> }; >> >> + ufs_mem_hc: ufs@1d84000 { >> + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", >> + "jedec,ufs-2.0"; >> + reg = <0x0 0x01d84000 0x0 0x3000>; >> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + lanes-per-direction = <2>; >> + #reset-cells = <1>; >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + power-domains = <&gcc GCC_UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x80 0x0>; >> + dma-coherent; >> + >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "rx_lane1_sync_clk"; > As discussed, property-names is preferred to come after > property, just like in the other node you're adding. Sure. Updated this in latest patchset and updated the binding as well. > > [...] > >> + ufs_mem_phy: phy@1d87000 { >> + compatible = "qcom,sc7280-qmp-ufs-phy"; >> + reg = <0x0 0x01d87000 0x0 0xe00>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + <&gcc GCC_UFS_1_CLKREF_EN>; >> + clock-names = "ref", "ref_aux", "qref"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + >> + }; > Stray newline above. Removed this in latest Patchset > > Konrad Thanks, Nitin
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 66f1eb83cca7..3be8ea090ade 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3353,6 +3353,70 @@ }; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x80 0x0>; + dma-coherent; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc7280-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sc7280-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
Add UFS host controller and PHY nodes for sc7280 soc. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.17.1