| Message ID | 20230927081858.15961-5-quic_nitirawa@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add UFS host controller and Phy nodes for sc7280 | expand |
Hi , I have reposted this patch by removing the change id. Please ignore this. Regards, Nitin On 9/27/2023 1:48 PM, Nitin Rawat wrote: > Align the binding property for clock such that "clocks" property > comes first followed by "clock-names" property. > > Change-Id: I53282da8eee8ec349d315de7ada56c99bb12b00d > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > .../devicetree/bindings/ufs/qcom,ufs.yaml | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index 802640efa956..d17bdc4e934f 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -295,14 +295,6 @@ examples: > <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; > interconnect-names = "ufs-ddr", "cpu-ufs"; > > - clock-names = "core_clk", > - "bus_aggr_clk", > - "iface_clk", > - "core_clk_unipro", > - "ref_clk", > - "tx_lane0_sync_clk", > - "rx_lane0_sync_clk", > - "rx_lane1_sync_clk"; > clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > <&gcc GCC_UFS_PHY_AHB_CLK>, > @@ -311,6 +303,14 @@ examples: > <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > freq-table-hz = <75000000 300000000>, > <0 0>, > <0 0>,
On 27.09.2023 10:29, Nitin Rawat wrote: > Hi , > I have reposted this patch by removing the change id. Please ignore this. > > Regards, > Nitin You resent this in a way that totally breaks threading: * cover letter v3 * patch 1 v3 * patch 2 v3 * patch 3 v3 * patch 4 v3 * patch 4 v3 For such minor changes, you can usually ask the maintainer to fix it up while applying - worst case scenario they'll ask you to resend the entire series. For the contents: Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 802640efa956..d17bdc4e934f 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -295,14 +295,6 @@ examples: <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -311,6 +303,14 @@ examples: <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; freq-table-hz = <75000000 300000000>, <0 0>, <0 0>,
Align the binding property for clock such that "clocks" property comes first followed by "clock-names" property. Change-Id: I53282da8eee8ec349d315de7ada56c99bb12b00d Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)