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Bottomley" , "Martin K. Petersen" CC: , , , Subject: [PATCH 2/3] scsi: ufs-qcom: Add support for dumping MCQ registers Date: Fri, 25 Oct 2024 11:20:53 +0530 Message-ID: <20241025055054.23170-3-quic_mapa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025055054.23170-1-quic_mapa@quicinc.com> References: <20241025055054.23170-1-quic_mapa@quicinc.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k1RulalwYd2ahtiPKGUNTVeUX3GbsYtn X-Proofpoint-ORIG-GUID: k1RulalwYd2ahtiPKGUNTVeUX3GbsYtn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxlogscore=826 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250043 This patch adds functionality to dump Multi-Queue (MCQ) registers. This will help in diagnosing issues related to MCQ operations by providing detailed register dumps. Signed-off-by: Manish Pandey --- drivers/ufs/host/ufs-qcom.c | 59 +++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 61 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 4752311b1f76..a43e818a7e14 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1480,6 +1480,52 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host) return 0; } +static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) +{ + /* RES_MCQ_1 */ + ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ HCI 1da0000-1da03f0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_2 */ + ufshcd_dump_regs(hba, 0x400, 256 * 4, "MCQ HCI 1da0400-1da07f0 "); + usleep_range(1000, 1100); + + /*RES_MCQ_VS */ + ufshcd_dump_regs(hba, 0x0, 5 * 4, "MCQ VS 1da4000-1da4010 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_1 */ + ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ SQD 1da5000-1da53f0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_2 */ + ufshcd_dump_regs(hba, 0x400, 256 * 4, "MCQ SQD 1da5400-1da57f0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_3 */ + ufshcd_dump_regs(hba, 0x800, 256 * 4, "MCQ SQD 1da5800-1da5bf0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_4 */ + ufshcd_dump_regs(hba, 0xc00, 256 * 4, "MCQ SQD 1da5c00-1da5ff0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_5 */ + ufshcd_dump_regs(hba, 0x1000, 256 * 4, "MCQ SQD 1da6000-1da63f0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_6 */ + ufshcd_dump_regs(hba, 0x1400, 256 * 4, "MCQ SQD 1da6400-1da67f0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_7 */ + ufshcd_dump_regs(hba, 0x1800, 256 * 4, "MCQ SQD 1da6800-1da6bf0 "); + usleep_range(1000, 1100); + + /* RES_MCQ_SQD_8 */ + ufshcd_dump_regs(hba, 0x1c00, 256 * 4, "MCQ SQD 1da6c00-1da6ff0 "); +} + static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) { u32 reg; @@ -1538,6 +1584,19 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); + + if (hba->mcq_enabled) { + reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); + ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); + } + + if (in_task()) { + /* Dump MCQ Host Vendor Specific Registers */ + if (hba->mcq_enabled) { + ufs_qcom_dump_mcq_hci_regs(hba); + usleep_range(1000, 1100); + } + } } /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 84e42fa123d2..980af902bab5 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -50,6 +50,8 @@ enum { */ UFS_AH8_CFG = 0xFC, + UFS_RD_REG_MCQ = 0xD00, + REG_UFS_CFG3 = 0x271C, REG_UFS_DEBUG_SPARE_CFG = 0x284C,