diff mbox series

[v2,1/2] scsi: ufs: export hibern8 entry and exit

Message ID a29bfdd0c8f1d1a3e5fb69e43ea277c97a7f0cb6.1632818942.git.nguyenb@codeaurora.org (mailing list archive)
State Accepted
Headers show
Series Put Qualcomm's ufs controller to hibern8 during clock scaling | expand

Commit Message

Bao D. Nguyen Sept. 28, 2021, 9:06 a.m. UTC
From: Asutosh Das <asutoshd@codeaurora.org>

Qualcomm controllers need to be in hibern8 before scaling up
or down the clocks. Hence, export the hibern8 entry and exit
functions.

Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Bao D. Nguyen <nguyenb@codeaurora.org>
---
 drivers/scsi/ufs/ufshcd.c | 4 ++--
 drivers/scsi/ufs/ufshcd.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

Comments

Bart Van Assche Sept. 28, 2021, 10:28 p.m. UTC | #1
On 9/28/21 2:06 AM, Bao D. Nguyen wrote:
> Qualcomm controllers need to be in hibern8 before scaling up
> or down the clocks. Hence, export the hibern8 entry and exit
> functions.
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Alim Akhtar Sept. 29, 2021, 3:13 a.m. UTC | #2
Hello,

>-----Original Message-----
>From: nguyenb=codeaurora.org@mg.codeaurora.org
>[mailto:nguyenb=codeaurora.org@mg.codeaurora.org] On Behalf Of Bao D.
>Nguyen
>Sent: Tuesday, September 28, 2021 2:36 PM
>To: cang@codeaurora.org; asutoshd@codeaurora.org;
>martin.petersen@oracle.com; linux-scsi@vger.kernel.org
>Cc: linux-arm-msm@vger.kernel.org; Bao D . Nguyen
><nguyenb@codeaurora.org>; Alim Akhtar <alim.akhtar@samsung.com>; Avri
>Altman <avri.altman@wdc.com>; James E.J. Bottomley <jejb@linux.ibm.com>;
>Bean Huo <beanhuo@micron.com>; Stanley Chu <stanley.chu@mediatek.com>;
>Bart Van Assche <bvanassche@acm.org>; Jaegeuk Kim <jaegeuk@kernel.org>;
>Adrian Hunter <adrian.hunter@intel.com>; Keoseong Park
><keosung.park@samsung.com>; open list <linux-kernel@vger.kernel.org>
>Subject: [PATCH v2 1/2] scsi: ufs: export hibern8 entry and exit
>
>From: Asutosh Das <asutoshd@codeaurora.org>
>
>Qualcomm controllers need to be in hibern8 before scaling up or down the
>clocks. Hence, export the hibern8 entry and exit functions.
>
>Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
>Signed-off-by: Bao D. Nguyen <nguyenb@codeaurora.org>
>---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> drivers/scsi/ufs/ufshcd.c | 4 ++--
> drivers/scsi/ufs/ufshcd.h | 1 +
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index
>3841ab49..f3aad32 100644
>--- a/drivers/scsi/ufs/ufshcd.c
>+++ b/drivers/scsi/ufs/ufshcd.c
>@@ -227,7 +227,6 @@ static void ufshcd_hba_exit(struct ufs_hba *hba);
static
>int ufshcd_clear_ua_wluns(struct ufs_hba *hba);  static int
>ufshcd_probe_hba(struct ufs_hba *hba, bool async);  static int
>ufshcd_setup_clocks(struct ufs_hba *hba, bool on); -static int
>ufshcd_uic_hibern8_enter(struct ufs_hba *hba);  static inline void
>ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);  static int
>ufshcd_host_reset_and_restore(struct ufs_hba *hba);  static void
>ufshcd_resume_clkscaling(struct ufs_hba *hba); @@ -4116,7 +4115,7 @@ int
>ufshcd_link_recovery(struct ufs_hba *hba)  }
>EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
>
>-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
>+int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
> {
> 	int ret;
> 	struct uic_command uic_cmd = {0};
>@@ -4138,6 +4137,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba
>*hba)
>
> 	return ret;
> }
>+EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
>
> int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)  { diff --git
>a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index
52ea6f3..124f50b
>100644
>--- a/drivers/scsi/ufs/ufshcd.h
>+++ b/drivers/scsi/ufs/ufshcd.h
>@@ -1001,6 +1001,7 @@ int ufshcd_init(struct ufs_hba *, void __iomem *,
>unsigned int);  int ufshcd_link_recovery(struct ufs_hba *hba);  int
>ufshcd_make_hba_operational(struct ufs_hba *hba);  void
ufshcd_remove(struct
>ufs_hba *);
>+int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
> int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);  void
>ufshcd_delay_us(unsigned long us, unsigned long tolerance);  int
>ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
>--
>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a
>Linux Foundation Collaborative Project
diff mbox series

Patch

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3841ab49..f3aad32 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -227,7 +227,6 @@  static void ufshcd_hba_exit(struct ufs_hba *hba);
 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
@@ -4116,7 +4115,7 @@  int ufshcd_link_recovery(struct ufs_hba *hba)
 }
 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
 
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
 {
 	int ret;
 	struct uic_command uic_cmd = {0};
@@ -4138,6 +4137,7 @@  static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
 
 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
 {
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 52ea6f3..124f50b 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -1001,6 +1001,7 @@  int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
 int ufshcd_link_recovery(struct ufs_hba *hba);
 int ufshcd_make_hba_operational(struct ufs_hba *hba);
 void ufshcd_remove(struct ufs_hba *);
+int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
 int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,