From patchwork Fri May 13 14:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ahmad Fatoum X-Patchwork-Id: 12848933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6A89C433FE for ; Fri, 13 May 2022 14:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381511AbiEMO6H (ORCPT ); Fri, 13 May 2022 10:58:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381551AbiEMO6E (ORCPT ); Fri, 13 May 2022 10:58:04 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 624F33DDD9 for ; Fri, 13 May 2022 07:58:00 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1npWjS-0002Ml-Bx; Fri, 13 May 2022 16:57:30 +0200 Received: from [2a0a:edc0:0:1101:1d::ac] (helo=dude04.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1npWjR-0026H6-Ln; Fri, 13 May 2022 16:57:28 +0200 Received: from afa by dude04.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1npWjP-008jCu-3j; Fri, 13 May 2022 16:57:27 +0200 From: Ahmad Fatoum To: =?utf-8?q?Horia_Geant=C4=83?= , Pankaj Gupta , Herbert Xu , "David S. Miller" Cc: kernel@pengutronix.de, Michael Walle , Ahmad Fatoum , James Bottomley , Jarkko Sakkinen , Mimi Zohar , David Howells , James Morris , Eric Biggers , "Serge E. Hallyn" , Jan Luebbe , David Gstir , Richard Weinberger , Franck LENORMAND , Matthias Schiffer , Sumit Garg , John Ernberg , linux-integrity@vger.kernel.org, keyrings@vger.kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-security-module@vger.kernel.org Subject: [PATCH v10 3/7] crypto: caam - determine whether CAAM supports blob encap/decap Date: Fri, 13 May 2022 16:57:01 +0200 Message-Id: <20220513145705.2080323-4-a.fatoum@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220513145705.2080323-1-a.fatoum@pengutronix.de> References: <20220513145705.2080323-1-a.fatoum@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: afa@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-security-module@vger.kernel.org Precedence: bulk List-ID: Depending on SoC variant, a CAAM may be available, but with some futures fused out. The LS1028A (non-E) SoC is one such SoC and while it indicates BLOB support, BLOB operations will ultimately fail, because there is no AES support. Add a new blob_present member to reflect whether both BLOB support and the AES support it depends on is available. These will be used in a follow-up commit to allow blob driver initialization to error out on SoCs without the necessary hardware support instead of failing at runtime with a cryptic caam_jr 8020000.jr: 20000b0f: CCB: desc idx 11: : Invalid CHA selected. Co-developed-by: Michael Walle Signed-off-by: Michael Walle Tested-by: Michael Walle # on ls1028a (non-E and E) Signed-off-by: Ahmad Fatoum Reviewed-by: Pankaj Gupta --- v9 -> v10: - added Michael's Tested-by - Check for AES support on CAAM era < 10, as LS1046A/LSA1012A have such CAAMs, which can be partially disabled. v8 -> v9: - New patch To: "Horia Geantă" To: Pankaj Gupta To: Herbert Xu To: "David S. Miller" Cc: James Bottomley Cc: Jarkko Sakkinen Cc: Mimi Zohar Cc: David Howells Cc: James Morris Cc: Eric Biggers Cc: "Serge E. Hallyn" Cc: Jan Luebbe Cc: David Gstir Cc: Richard Weinberger Cc: Franck LENORMAND Cc: Matthias Schiffer Cc: Sumit Garg Cc: Michael Walle Cc: John Ernberg Cc: linux-integrity@vger.kernel.org Cc: keyrings@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-security-module@vger.kernel.org --- drivers/crypto/caam/ctrl.c | 17 +++++++++++++++-- drivers/crypto/caam/intern.h | 1 + drivers/crypto/caam/regs.h | 4 +++- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index ca0361b2dbb0..38c4d88a9d03 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -820,12 +820,25 @@ static int caam_probe(struct platform_device *pdev) return -ENOMEM; } - if (ctrlpriv->era < 10) + comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ls); + ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB); + + /* + * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support, + * but fail when actually using it due to missing AES support, so + * check both here. + */ + if (ctrlpriv->era < 10) { rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; - else + ctrlpriv->blob_present = ctrlpriv->blob_present && + (rd_reg32(&ctrl->perfmon.cha_num_ls) & CHA_ID_LS_AES_MASK); + } else { rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; + ctrlpriv->blob_present = ctrlpriv->blob_present && + (rd_reg32(&ctrl->vreg.aesa) & CHA_VER_MISC_AES_NUM_MASK); + } /* * If SEC has RNG version >= 4 and RNG state handle has not been diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h index 7d45b21bd55a..e92210e2ab76 100644 --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h @@ -92,6 +92,7 @@ struct caam_drv_private { */ u8 total_jobrs; /* Total Job Rings in device */ u8 qi_present; /* Nonzero if QI present in device */ + u8 blob_present; /* Nonzero if BLOB support present in device */ u8 mc_en; /* Nonzero if MC f/w is active */ int secvio_irq; /* Security violation interrupt number */ int virt_en; /* Virtualization enabled in CAAM */ diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 3738625c0250..66d6dad841bb 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -320,7 +320,8 @@ struct version_regs { #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT) /* CHA Miscellaneous Information - AESA_MISC specific */ -#define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) +#define CHA_VER_MISC_AES_NUM_MASK GENMASK(7, 0) +#define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) /* CHA Miscellaneous Information - PKHA_MISC specific */ #define CHA_VER_MISC_PKHA_NO_CRYPT BIT(7 + CHA_VER_MISC_SHIFT) @@ -414,6 +415,7 @@ struct caam_perfmon { #define CTPR_MS_PG_SZ_MASK 0x10 #define CTPR_MS_PG_SZ_SHIFT 4 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ +#define CTPR_LS_BLOB BIT(1) u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ u64 rsvd1[2];