From patchwork Fri Dec 18 02:29:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 7878361 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C7EF39F1C2 for ; Fri, 18 Dec 2015 02:29:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EBDA22040F for ; Fri, 18 Dec 2015 02:29:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0AF4920443 for ; Fri, 18 Dec 2015 02:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966071AbbLRC31 (ORCPT ); Thu, 17 Dec 2015 21:29:27 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38915 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966038AbbLRC31 (ORCPT ); Thu, 17 Dec 2015 21:29:27 -0500 Received: from reginn.isobedori.kobe.vergenet.net (p1027-ipbfp1401kobeminato.hyogo.ocn.ne.jp [114.152.28.27]) by kirsty.vergenet.net (Postfix) with ESMTPA id 8449625BE72; Fri, 18 Dec 2015 13:29:22 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1450405762; bh=U2wyCUDE3zNP3VbTMStTU0Ns8NDSrUJ3nFXYc4I+41Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cfwLWJDq9+tGxTx7ihbxnrYeIDYV9ynpxlfNS0pmFDDIt5lJvY931U7K5isY3X2rx TwprSlyyKGuQZlYwp5pJlqw79UM2DN8j6Vu1+N0zEuup3RSJuCmWuWpOstkT8ARtjZ vE7ZSnMEdbJZkwEwFoIUtWSpn8E8dEfumZaHJVnA= Received: by reginn.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id F02E4940830; Fri, 18 Dec 2015 11:29:20 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Gaku Inami , Takeshi Kihara , Simon Horman Subject: [PATCH 04/10] arm64: dts: r8a7795: Add Cortex-A57 CPU cores Date: Fri, 18 Dec 2015 11:29:12 +0900 Message-Id: <0ed1a79ed0c17631fb41d336a4eddb9bbd299b64.1450401186.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaku Inami Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. Signed-off-by: Gaku Inami Signed-off-by: Takeshi Kihara Sigend-off-by: Dirk Behme Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 051ff143506e..4d43cf31418f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -35,13 +35,31 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; enable-method = "psci"; }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_2: cpu@2 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_3: cpu@3 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; }; extal_clk: extal { @@ -84,6 +102,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -96,7 +115,7 @@ reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x2000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { @@ -214,13 +233,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller@e6150000 {