From patchwork Mon Aug 22 15:56:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 1085892 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7MFvrTC016437 for ; Mon, 22 Aug 2011 15:57:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752185Ab1HVP5x (ORCPT ); Mon, 22 Aug 2011 11:57:53 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:52693 "EHLO relmlor1.renesas.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752121Ab1HVP5w (ORCPT ); Mon, 22 Aug 2011 11:57:52 -0400 Received: from relmlir1.idc.renesas.com ([10.200.68.151]) by relmlor1.idc.renesas.com ( SJSMS) with ESMTP id <0LQC00JZK70FPE60@relmlor1.idc.renesas.com> for linux-sh@vger.kernel.org; Tue, 23 Aug 2011 00:57:51 +0900 (JST) Received: from relmlac4.idc.renesas.com ([10.200.69.24]) by relmlir1.idc.renesas.com (SJSMS) with ESMTP id <0LQC00KCJ70F1M70@relmlir1.idc.renesas.com> for linux-sh@vger.kernel.org; Tue, 23 Aug 2011 00:57:51 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 707EC4807B; Tue, 23 Aug 2011 00:57:51 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 6A14348070 for ; Tue, 23 Aug 2011 00:57:51 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id AAA10632; Tue, 23 Aug 2011 00:57:51 +0900 X-IronPort-AV: E=Sophos; i="4.68,263,1312124400"; d="scan'208"; a="42014058" Received: from unknown (HELO rte-idc-bh1.RTE.ADWIN.RENESAS.COM) ([172.28.64.243]) by relmlii2.idc.renesas.com with ESMTP; Tue, 23 Aug 2011 00:57:50 +0900 Received: from rte-ben-exch.RTE.ADWIN.RENESAS.COM ([172.29.42.16]) by rte-idc-bh1.RTE.ADWIN.RENESAS.COM with Microsoft SMTPSVC(6.0.3790.211) ; Mon, 22 Aug 2011 16:57:48 +0100 Received: from localhost.localdomain ([172.29.43.116]) by rte-ben-exch.RTE.ADWIN.RENESAS.COM with Microsoft SMTPSVC(6.0.3790.3959) ; Mon, 22 Aug 2011 16:57:47 +0100 From: Phil Edworthy To: linux-sh@vger.kernel.org Cc: Phil Edworthy Subject: [PATCH 2/2] sh: Add unaligned memory access for PC relative intructions Date: Mon, 22 Aug 2011 16:56:37 +0100 Message-id: <1314028597-7612-1-git-send-email-phil.edworthy@renesas.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 22 Aug 2011 15:57:47.0459 (UTC) FILETIME=[3CBAD930:01CC60E4] Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 22 Aug 2011 15:57:53 +0000 (UTC) This add unaligned memory access support for the following instructions: mov.w @(disp,PC),Rn mov.l @(disp,PC),Rn These instructions are often used on SH2A toolchains. Signed-off-by: Phil Edworthy --- arch/sh/kernel/traps_32.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c index 61fa4a5..957c506 100644 --- a/arch/sh/kernel/traps_32.c +++ b/arch/sh/kernel/traps_32.c @@ -316,6 +316,37 @@ static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, break; } break; + + case 9: /* mov.w @(disp,PC),Rn */ + srcu = (unsigned char __user *)regs->pc; + srcu += (instruction & 0x00FF) << 1; + dst = (unsigned char *)rn; + *(unsigned long *)dst = 0; + +#if !defined(__LITTLE_ENDIAN__) + dst += 2; +#endif + + if (ma->from(dst, srcu, 2)) + goto fetch_fault; + sign_extend(2, dst); + ret = 0; + break; + + case 0xd: /* mov.l @(disp,PC),Rn */ + srcu = (unsigned char __user *)regs->pc; + srcu += (instruction & 0x00FF) << 2; + dst = (unsigned char *)rn; + *(unsigned long *)dst = 0; + +#if !defined(__LITTLE_ENDIAN__) + dst += 2; +#endif + + if (ma->from(dst, srcu, 4)) + goto fetch_fault; + ret = 0; + break; } return ret; @@ -496,6 +527,9 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, } break; + case 0x9000: /* mov.w @(disp,Rm),Rn */ + goto simple; + case 0xA000: /* bra label */ ret = handle_delayslot(regs, instruction, ma); if (ret==0) @@ -509,6 +543,9 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, regs->pc += SH_PC_12BIT_OFFSET(instruction); } break; + + case 0xD000: /* mov.l @(disp,Rm),Rn */ + goto simple; } return ret;