From patchwork Thu Dec 6 12:08:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Hecht X-Patchwork-Id: 1844761 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id AF693DF2F9 for ; Thu, 6 Dec 2012 12:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752746Ab2LFMIq (ORCPT ); Thu, 6 Dec 2012 07:08:46 -0500 Received: from mail-ea0-f174.google.com ([209.85.215.174]:52664 "EHLO mail-ea0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752672Ab2LFMIp (ORCPT ); Thu, 6 Dec 2012 07:08:45 -0500 Received: by mail-ea0-f174.google.com with SMTP id e13so2457266eaa.19 for ; Thu, 06 Dec 2012 04:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=7v0XiVkSkCeafJQl7F364xZXnbkY8m0uhoBO+GPsGh4=; b=S6A5LHb8I2Sn/MBjkcsTrCm2CBgqUNQUrHj9ZsKQsWN8OYB5VH7UkiSMmOiFhiZvQZ 3AlYB9pjzCNQ6p77tuDYUauqDqZEEylm4rKkP2s8rnMxRQKkjHF8+IyECIVDo1sVkeSa iK+3ibz07nko372t707dkyMwtYYTHX3K74uLBNpv/RxvTH+pPVs96imIMZ8l9hGaleYi HEx8WIPAQoEQxQLBF9+qt8Xgodst5ZP5sxN+XiulGPnTSpl2IFH8+o2lPObriElTR2Qt Hmcd5G0+lGL3k1LePzw9UHM7jevsolKsFWOgS/9ZCymn9Cw0+sQ2XmGSiaUmMFMk9cAb i+Fw== Received: by 10.14.205.198 with SMTP id j46mr5089125eeo.27.1354795724406; Thu, 06 Dec 2012 04:08:44 -0800 (PST) Received: from localhost.localdomain (p4FD26E52.dip.t-dialin.net. [79.210.110.82]) by mx.google.com with ESMTPS id 44sm15568919eek.0.2012.12.06.04.08.43 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Dec 2012 04:08:44 -0800 (PST) From: Bastian Hecht To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH 2/2] ARM: SH-Mobile: sh73a0: Add CPU Hotplug Date: Thu, 6 Dec 2012 13:08:39 +0100 Message-Id: <1354795719-5578-2-git-send-email-hechtb+renesas@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354795719-5578-1-git-send-email-hechtb+renesas@gmail.com> References: <1354795719-5578-1-git-send-email-hechtb+renesas@gmail.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org From: Bastian Hecht Add the capability to add and remove CPUs on the fly. The Cortex-A9 offers the possibility to take single cores out of the MP Core. We add this capabilty taking care that caches are kept coherent. For the actual shutdown via a WFI instruction, a code snippet from the omap2 code tree is copied. Thanks for that! For verifying the shutdown we rely on the internal SH73A0 Power Status Register PSTR. Signed-off-by: Bastian Hecht Acked-by: Magnus Damm --- arch/arm/mach-shmobile/headsmp-sh73a0.S | 46 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/smp-sh73a0.c | 41 +++++++++++++++++++---- 3 files changed, 82 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-sh73a0.S index bec4c0d..be463a3 100644 --- a/arch/arm/mach-shmobile/headsmp-sh73a0.S +++ b/arch/arm/mach-shmobile/headsmp-sh73a0.S @@ -23,6 +23,52 @@ #include #include +/* Taken from arch/arm/mach-omap2/sleep44xx.S. Thanks! */ +ENTRY(sh73a0_do_wfi) + stmfd sp!, {lr} + + /* + * Execute an ISB instruction to ensure that all of the + * CP15 register changes have been committed. + */ + isb + + /* + * Execute a barrier instruction to ensure that all cache, + * TLB and branch predictor maintenance operations issued + * by any CPU in the cluster have completed. + */ + dsb + dmb + + /* + * Execute a WFI instruction and wait until the + * STANDBYWFI output is asserted to indicate that the + * CPU is in idle and low power state. CPU can specualatively + * prefetch the instructions so add NOPs after WFI. Sixteen + * NOPs as per Cortex-A9 pipeline. + */ + wfi @ Wait For Interrupt + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + ldmfd sp!, {pc} +ENDPROC(sh73a0_do_wfi) + __CPUINIT /* * Reset vector for secondary CPUs. diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index f2e2c29..40f767e 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -55,6 +55,7 @@ extern void sh73a0_add_standard_devices(void); extern void sh73a0_clock_init(void); extern void sh73a0_pinmux_init(void); extern void sh73a0_secondary_vector(void); +extern void sh73a0_do_wfi(void); extern struct clk sh73a0_extal1_clk; extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 5e36f5d..9237e13 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,8 @@ #define SBAR IOMEM(0xe6180020) #define APARMBAREA IOMEM(0xe6f10020) +#define PSTR_SHUTDOWN_MODE 3 + static void __iomem *scu_base_addr(void) { return (void __iomem *)0xf0000000; @@ -92,16 +95,20 @@ static void __init sh73a0_smp_init_cpus(void) shmobile_smp_init_cpus(ncores); } -static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu) +#ifdef CONFIG_HOTPLUG_CPU +static int sh73a0_cpu_kill(unsigned int cpu) { + int k; + u32 pstr; - /* this function is running on another CPU than the offline target, - * here we need wait for shutdown code in platform_cpu_die() to - * finish before asking SoC-specific code to power off the CPU core. + /* + * wait until the power status register confirms the shutdown of the + * offline target */ for (k = 0; k < 1000; k++) { - if (shmobile_cpu_is_dead(cpu)) + pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3; + if (pstr == PSTR_SHUTDOWN_MODE) return 1; mdelay(1); @@ -110,6 +117,28 @@ static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu) return 0; } +static void sh73a0_cpu_die(unsigned int cpu) +{ + /* + * The ARM MPcore does not issue a cache coherency request for the L1 + * cache when powering off single CPUs. We must take care of this and + * further caches. + */ + dsb(); + flush_cache_all(); + + /* Set power off mode. This takes the CPU out of the MP cluster */ + scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); + + /* Enter shutdown mode */ + sh73a0_do_wfi(); + + /* We assume success always. We never reach this */ + pr_err("Shutting down CPU failed. This should never happen!\n"); + for (;;) + ; +} +#endif /* CONFIG_HOTPLUG_CPU */ struct smp_operations sh73a0_smp_ops __initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, @@ -118,7 +147,7 @@ struct smp_operations sh73a0_smp_ops __initdata = { .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill, - .cpu_die = shmobile_cpu_die, + .cpu_die = sh73a0_cpu_die, .cpu_disable = shmobile_cpu_disable, #endif };