From patchwork Fri Jun 21 07:10:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2760511 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8946BC0AB1 for ; Fri, 21 Jun 2013 07:11:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 92EB3200F4 for ; Fri, 21 Jun 2013 07:11:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8338F200EC for ; Fri, 21 Jun 2013 07:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758745Ab3FUHLS (ORCPT ); Fri, 21 Jun 2013 03:11:18 -0400 Received: from moutng.kundenserver.de ([212.227.126.186]:54531 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758744Ab3FUHLR (ORCPT ); Fri, 21 Jun 2013 03:11:17 -0400 Received: from axis700.grange (dslb-084-061-108-118.pools.arcor-ip.net [84.61.108.118]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0Ls7Op-1UA9aq17Fv-013MWk; Fri, 21 Jun 2013 09:10:39 +0200 Received: from 6a.grange (6a.grange [192.168.1.11]) by axis700.grange (Postfix) with ESMTPS id CB41440BB3; Fri, 21 Jun 2013 09:10:38 +0200 (CEST) Received: from lyakh by 6a.grange with local (Exim 4.72) (envelope-from ) id 1UpvUU-0002kQ-HZ; Fri, 21 Jun 2013 09:10:38 +0200 From: Guennadi Liakhovetski To: linux-sh@vger.kernel.org Cc: Magnus Damm , Simon Horman , linux-arm-kernel@lists.infradead.org, Guennadi Liakhovetski Subject: [PATCH 4/4] ARM: shmobile: r8a73a4: add Z2 clock support Date: Fri, 21 Jun 2013 09:10:38 +0200 Message-Id: <1371798638-10530-5-git-send-email-g.liakhovetski@gmx.de> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1371798638-10530-1-git-send-email-g.liakhovetski@gmx.de> References: <1371798638-10530-1-git-send-email-g.liakhovetski@gmx.de> X-Provags-ID: V02:K0:0jnPWL2o++sw+jn6jjVcAQOeUtB5sffLL49/f0JH+FY yYrf1fKxTohpVFCnySZrFIWoWZZlnUjHZOxhlEOhbv+QUk4MAy dkhtj0fCC1Q2qm12F7b1ywPTqowjcZpCSqe0mNH+nZeVLSIXzP 0HP/b1j/5timUH7kAbfVD4idoXuvP0nBY3Tq5RXp3y5PSFID0N RQ3SS1Od2zUYL8uDVIorbZPGo/iQhnJddz1x6b/6J440Gatzhv hKQscc6v9Nj+9Iq4bP7p3iHs8x22XdAk13uCg/szBB4BSqsve0 pMpYEYljsdPgYsjqsEYDWDqWlyi/waWOWb6PSplaVT5m8+HX0y 5JXUKmbZwwO3vuPSX9XNsz0CQqee34A72BoZfA14Z3iUeZPo0J CKrwWDvWDpxag== Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Z2 clock on r8a73a4 is used to clock the 4 Cortex A7 cores on the SoC. Add a definition for this clock to later use it from the arm_big_little CPUFreq driver. Signed-off-by: Guennadi Liakhovetski --- arch/arm/mach-shmobile/clock-r8a73a4.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 508cb1e..b717e98 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -324,6 +324,21 @@ static struct clk z_clk = { .ops = &zclk_ops, }; +/* + * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3 + * switching is only available in auto-DVFS mode + */ +SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2); + +static struct clk z2_clk = { + .parent = &pll0_div2_clk, + .div_mask = 0x1f, + .enable_bit = 0, + /* We'll need to access FRQCRB and FRQCRC */ + .enable_reg = (void __iomem *)FRQCRB, + .ops = &zclk_ops, +}; + static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, @@ -342,6 +357,8 @@ static struct clk *main_clks[] = { &pll2s_clk, &pll2h_clk, &z_clk, + &pll0_div2_clk, + &z2_clk, }; /* DIV4 */