diff mbox

[2/4] ARM: shmobile: r8a7790: add I2C support in Device Tree mode

Message ID 1378742636-11215-3-git-send-email-g.liakhovetski@gmx.de (mailing list archive)
State Changes Requested
Headers show

Commit Message

Guennadi Liakhovetski Sept. 9, 2013, 4:03 p.m. UTC
This patch adds clocks and clock lookup entries for the four I2C
controllers on r8a7790 and respective Device Tree nodes.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
---
 arch/arm/boot/dts/r8a7790.dtsi         |   36 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

Comments

Laurent Pinchart Sept. 25, 2013, 8:52 a.m. UTC | #1
Hi Guennadi,

Thank you for the patch.

On Monday 09 September 2013 18:03:54 Guennadi Liakhovetski wrote:
> This patch adds clocks and clock lookup entries for the four I2C
> controllers on r8a7790 and respective Device Tree nodes.
> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
> ---
>  arch/arm/boot/dts/r8a7790.dtsi         |   36 +++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
>  2 files changed, 46 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index 885f9f4..a5021112 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -127,6 +127,42 @@
>  		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>;
>  	};
> 
> +	i2c0: i2c@e6508000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6508000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 287 0x4>;

Shouldn't you add state = "disabled" to all I2C controllers in order not to 
enable the unused controllers by default ?

> +	};
> +
> +	i2c1: i2c@e6518000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6518000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 288 0x4>;
> +	};
> +
> +	i2c2: i2c@e6530000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6530000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 286 0x4>;
> +	};
> +
> +	i2c3: i2c@e6540000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6540000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 290 0x4>;
> +	};
> +
>  	mmcif0: mmcif@ee200000 {
>  		compatible = "renesas,sh-mmcif";
>  		reg = <0 0xee200000 0 0x80>;
> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c
> b/arch/arm/mach-shmobile/clock-r8a7790.c index fc36d3d..8e5e90b 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> @@ -52,6 +52,7 @@
>  #define SMSTPCR5 0xe6150144
>  #define SMSTPCR7 0xe615014c
>  #define SMSTPCR8 0xe6150990
> +#define SMSTPCR9 0xe6150994
> 
>  #define SDCKCR		0xE6150074
>  #define SD2CKCR		0xE6150078
> @@ -181,6 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
> 
>  /* MSTP */
>  enum {
> +	MSTP931, MSTP930, MSTP929, MSTP928,
>  	MSTP813,
>  	MSTP721, MSTP720,
>  	MSTP717, MSTP716,
> @@ -192,6 +194,10 @@ enum {
>  };
> 
>  static struct clk mstp_clks[MSTP_NR] = {
> +	[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
> +	[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
> +	[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
> +	[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
>  	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
>  	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
>  	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
> @@ -261,6 +267,10 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
>  	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
>  	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
> +	CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
> +	CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
> +	CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
> +	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
>  	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
>  	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
>  	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
Guennadi Liakhovetski Sept. 25, 2013, 10:10 p.m. UTC | #2
Hi Laurent

On Wed, 25 Sep 2013, Laurent Pinchart wrote:

> Hi Guennadi,
> 
> Thank you for the patch.
> 
> On Monday 09 September 2013 18:03:54 Guennadi Liakhovetski wrote:
> > This patch adds clocks and clock lookup entries for the four I2C
> > controllers on r8a7790 and respective Device Tree nodes.
> > 
> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
> > ---
> >  arch/arm/boot/dts/r8a7790.dtsi         |   36 +++++++++++++++++++++++++++++
> >  arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
> >  2 files changed, 46 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> > index 885f9f4..a5021112 100644
> > --- a/arch/arm/boot/dts/r8a7790.dtsi
> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
> > @@ -127,6 +127,42 @@
> >  		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>;
> >  	};
> > 
> > +	i2c0: i2c@e6508000 {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		compatible = "renesas,i2c-rcar-h2";
> > +		reg = <0 0xe6508000 0 0x40>;
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <0 287 0x4>;
> 
> Shouldn't you add state = "disabled" to all I2C controllers in order not to 
> enable the unused controllers by default ?

It would be logical, yes, and I seem to remember having discussed this 
earlier with someone (with Magnus, IIRC), and the outcome was, that all 
Renesas .dtsi files so far define all I2C directly in enabled mode and 
that it's intentional, so, I just followed this pattern here. You can 
indeed check in other .dtsi files - all seem to do exactly the same.

Thanks
Guennadi

> 
> > +	};
> > +
> > +	i2c1: i2c@e6518000 {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		compatible = "renesas,i2c-rcar-h2";
> > +		reg = <0 0xe6518000 0 0x40>;
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <0 288 0x4>;
> > +	};
> > +
> > +	i2c2: i2c@e6530000 {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		compatible = "renesas,i2c-rcar-h2";
> > +		reg = <0 0xe6530000 0 0x40>;
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <0 286 0x4>;
> > +	};
> > +
> > +	i2c3: i2c@e6540000 {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		compatible = "renesas,i2c-rcar-h2";
> > +		reg = <0 0xe6540000 0 0x40>;
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <0 290 0x4>;
> > +	};
> > +
> >  	mmcif0: mmcif@ee200000 {
> >  		compatible = "renesas,sh-mmcif";
> >  		reg = <0 0xee200000 0 0x80>;
> > diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c
> > b/arch/arm/mach-shmobile/clock-r8a7790.c index fc36d3d..8e5e90b 100644
> > --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> > +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> > @@ -52,6 +52,7 @@
> >  #define SMSTPCR5 0xe6150144
> >  #define SMSTPCR7 0xe615014c
> >  #define SMSTPCR8 0xe6150990
> > +#define SMSTPCR9 0xe6150994
> > 
> >  #define SDCKCR		0xE6150074
> >  #define SD2CKCR		0xE6150078
> > @@ -181,6 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
> > 
> >  /* MSTP */
> >  enum {
> > +	MSTP931, MSTP930, MSTP929, MSTP928,
> >  	MSTP813,
> >  	MSTP721, MSTP720,
> >  	MSTP717, MSTP716,
> > @@ -192,6 +194,10 @@ enum {
> >  };
> > 
> >  static struct clk mstp_clks[MSTP_NR] = {
> > +	[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
> > +	[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
> > +	[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
> > +	[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
> >  	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
> >  	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
> >  	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
> > @@ -261,6 +267,10 @@ static struct clk_lookup lookups[] = {
> >  	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
> >  	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
> >  	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
> > +	CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
> > +	CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
> > +	CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
> > +	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
> >  	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
> >  	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> >  	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
> -- 
> Regards,
> 
> Laurent Pinchart
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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Simon Horman Sept. 26, 2013, 1:49 a.m. UTC | #3
On Mon, Sep 09, 2013 at 06:03:54PM +0200, Guennadi Liakhovetski wrote:
> This patch adds clocks and clock lookup entries for the four I2C
> controllers on r8a7790 and respective Device Tree nodes.
> 
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
> ---
>  arch/arm/boot/dts/r8a7790.dtsi         |   36 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
>  2 files changed, 46 insertions(+), 0 deletions(-)

Hi Guennadi,

please split this patch into two patches.
1. A SoC patch which updates clock-r8a7790.c
2. A DT patch which updates r8a7790.dtsi

Thanks

> 
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index 885f9f4..a5021112 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -127,6 +127,42 @@
>  		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>;
>  	};
>  
> +	i2c0: i2c@e6508000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6508000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 287 0x4>;
> +	};
> +
> +	i2c1: i2c@e6518000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6518000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 288 0x4>;
> +	};
> +
> +	i2c2: i2c@e6530000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6530000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 286 0x4>;
> +	};
> +
> +	i2c3: i2c@e6540000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,i2c-rcar-h2";
> +		reg = <0 0xe6540000 0 0x40>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 290 0x4>;
> +	};
> +
>  	mmcif0: mmcif@ee200000 {
>  		compatible = "renesas,sh-mmcif";
>  		reg = <0 0xee200000 0 0x80>;
> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> index fc36d3d..8e5e90b 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> @@ -52,6 +52,7 @@
>  #define SMSTPCR5 0xe6150144
>  #define SMSTPCR7 0xe615014c
>  #define SMSTPCR8 0xe6150990
> +#define SMSTPCR9 0xe6150994
>  
>  #define SDCKCR		0xE6150074
>  #define SD2CKCR		0xE6150078
> @@ -181,6 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
>  
>  /* MSTP */
>  enum {
> +	MSTP931, MSTP930, MSTP929, MSTP928,
>  	MSTP813,
>  	MSTP721, MSTP720,
>  	MSTP717, MSTP716,
> @@ -192,6 +194,10 @@ enum {
>  };
>  
>  static struct clk mstp_clks[MSTP_NR] = {
> +	[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
> +	[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
> +	[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
> +	[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
>  	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
>  	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
>  	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
> @@ -261,6 +267,10 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
>  	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
>  	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
> +	CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
> +	CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
> +	CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
> +	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
>  	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
>  	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
>  	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
> -- 
> 1.7.2.5
> 
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Magnus Damm Sept. 26, 2013, 4:05 a.m. UTC | #4
Hi Guennadi,

On Thu, Sep 26, 2013 at 7:10 AM, Guennadi Liakhovetski
<g.liakhovetski@gmx.de> wrote:
> Hi Laurent
>
> On Wed, 25 Sep 2013, Laurent Pinchart wrote:
>
>> Hi Guennadi,
>>
>> Thank you for the patch.
>>
>> On Monday 09 September 2013 18:03:54 Guennadi Liakhovetski wrote:
>> > This patch adds clocks and clock lookup entries for the four I2C
>> > controllers on r8a7790 and respective Device Tree nodes.
>> >
>> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
>> > ---
>> >  arch/arm/boot/dts/r8a7790.dtsi         |   36 +++++++++++++++++++++++++++++
>> >  arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
>> >  2 files changed, 46 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
>> > index 885f9f4..a5021112 100644
>> > --- a/arch/arm/boot/dts/r8a7790.dtsi
>> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> > @@ -127,6 +127,42 @@
>> >             interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
>> >     };
>> >
>> > +   i2c0: i2c@e6508000 {
>> > +           #address-cells = <1>;
>> > +           #size-cells = <0>;
>> > +           compatible = "renesas,i2c-rcar-h2";
>> > +           reg = <0 0xe6508000 0 0x40>;
>> > +           interrupt-parent = <&gic>;
>> > +           interrupts = <0 287 0x4>;
>>
>> Shouldn't you add state = "disabled" to all I2C controllers in order not to
>> enable the unused controllers by default ?
>
> It would be logical, yes, and I seem to remember having discussed this
> earlier with someone (with Magnus, IIRC), and the outcome was, that all
> Renesas .dtsi files so far define all I2C directly in enabled mode and
> that it's intentional, so, I just followed this pattern here. You can
> indeed check in other .dtsi files - all seem to do exactly the same.

Uhm, I think you mix up platform device use case and DT use case. In
the platform device case we define all devices by default, but that's
not how it should be for the DT case. In the case of DT then default
should most likely be "disabled". Please follow the direction of
Laurent.

Also, I mentioned this 25 times before already so once more cannot
hurt: "renesas,i2c-rcar-h2" needs to be replaced with something more
standard.

/ magnus
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Guennadi Liakhovetski Sept. 26, 2013, 7:07 a.m. UTC | #5
Hi Magnus

On Thu, 26 Sep 2013, Magnus Damm wrote:

> Hi Guennadi,
> 
> On Thu, Sep 26, 2013 at 7:10 AM, Guennadi Liakhovetski
> <g.liakhovetski@gmx.de> wrote:
> > Hi Laurent
> >
> > On Wed, 25 Sep 2013, Laurent Pinchart wrote:
> >
> >> Hi Guennadi,
> >>
> >> Thank you for the patch.
> >>
> >> On Monday 09 September 2013 18:03:54 Guennadi Liakhovetski wrote:
> >> > This patch adds clocks and clock lookup entries for the four I2C
> >> > controllers on r8a7790 and respective Device Tree nodes.
> >> >
> >> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
> >> > ---
> >> >  arch/arm/boot/dts/r8a7790.dtsi         |   36 +++++++++++++++++++++++++++++
> >> >  arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
> >> >  2 files changed, 46 insertions(+), 0 deletions(-)
> >> >
> >> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> >> > index 885f9f4..a5021112 100644
> >> > --- a/arch/arm/boot/dts/r8a7790.dtsi
> >> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
> >> > @@ -127,6 +127,42 @@
> >> >             interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
> >> >     };
> >> >
> >> > +   i2c0: i2c@e6508000 {
> >> > +           #address-cells = <1>;
> >> > +           #size-cells = <0>;
> >> > +           compatible = "renesas,i2c-rcar-h2";
> >> > +           reg = <0 0xe6508000 0 0x40>;
> >> > +           interrupt-parent = <&gic>;
> >> > +           interrupts = <0 287 0x4>;
> >>
> >> Shouldn't you add state = "disabled" to all I2C controllers in order not to
> >> enable the unused controllers by default ?
> >
> > It would be logical, yes, and I seem to remember having discussed this
> > earlier with someone (with Magnus, IIRC), and the outcome was, that all
> > Renesas .dtsi files so far define all I2C directly in enabled mode and
> > that it's intentional, so, I just followed this pattern here. You can
> > indeed check in other .dtsi files - all seem to do exactly the same.
> 
> Uhm, I think you mix up platform device use case and DT use case.

I'm sure I don't.

> In
> the platform device case we define all devices by default, but that's
> not how it should be for the DT case. In the case of DT then default
> should most likely be "disabled". Please follow the direction of
> Laurent.

To put the record straight - originally I suggested to use status 
"disabled" for mmc devices in .dtsi, before that the status property 
wasn't used in Renesas .dts(i) files, and that's when all I2C nodes were 
already present in .dtsi in enabled state.

> Also, I mentioned this 25 times before already so once more cannot
> hurt: "renesas,i2c-rcar-h2" needs to be replaced with something more
> standard.

I didn't count, but yes, it has been discussed and that's been fixed in v2 
of my i2c patches. Now that I've got comments to the ARM patches I can 
also update them with a correct compatibility string.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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Magnus Damm Sept. 26, 2013, 9:32 a.m. UTC | #6
Hi Guennadi,

On Thu, Sep 26, 2013 at 12:07 AM, Guennadi Liakhovetski
<g.liakhovetski@gmx.de> wrote:
> Hi Magnus
>
> On Thu, 26 Sep 2013, Magnus Damm wrote:
>
>> Hi Guennadi,
>>
>> On Thu, Sep 26, 2013 at 7:10 AM, Guennadi Liakhovetski
>> <g.liakhovetski@gmx.de> wrote:
>> > Hi Laurent
>> >
>> > On Wed, 25 Sep 2013, Laurent Pinchart wrote:
>> >
>> >> Hi Guennadi,
>> >>
>> >> Thank you for the patch.
>> >>
>> >> On Monday 09 September 2013 18:03:54 Guennadi Liakhovetski wrote:
>> >> > This patch adds clocks and clock lookup entries for the four I2C
>> >> > controllers on r8a7790 and respective Device Tree nodes.
>> >> >
>> >> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
>> >> > ---
>> >> >  arch/arm/boot/dts/r8a7790.dtsi         |   36 +++++++++++++++++++++++++++++
>> >> >  arch/arm/mach-shmobile/clock-r8a7790.c |   10 ++++++++
>> >> >  2 files changed, 46 insertions(+), 0 deletions(-)
>> >> >
>> >> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
>> >> > index 885f9f4..a5021112 100644
>> >> > --- a/arch/arm/boot/dts/r8a7790.dtsi
>> >> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> >> > @@ -127,6 +127,42 @@
>> >> >             interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
>> >> >     };
>> >> >
>> >> > +   i2c0: i2c@e6508000 {
>> >> > +           #address-cells = <1>;
>> >> > +           #size-cells = <0>;
>> >> > +           compatible = "renesas,i2c-rcar-h2";
>> >> > +           reg = <0 0xe6508000 0 0x40>;
>> >> > +           interrupt-parent = <&gic>;
>> >> > +           interrupts = <0 287 0x4>;
>> >>
>> >> Shouldn't you add state = "disabled" to all I2C controllers in order not to
>> >> enable the unused controllers by default ?
>> >
>> > It would be logical, yes, and I seem to remember having discussed this
>> > earlier with someone (with Magnus, IIRC), and the outcome was, that all
>> > Renesas .dtsi files so far define all I2C directly in enabled mode and
>> > that it's intentional, so, I just followed this pattern here. You can
>> > indeed check in other .dtsi files - all seem to do exactly the same.
>>
>> Uhm, I think you mix up platform device use case and DT use case.
>
> I'm sure I don't.

Ok, but it sure sounds like that.

>> In
>> the platform device case we define all devices by default, but that's
>> not how it should be for the DT case. In the case of DT then default
>> should most likely be "disabled". Please follow the direction of
>> Laurent.
>
> To put the record straight - originally I suggested to use status
> "disabled" for mmc devices in .dtsi, before that the status property
> wasn't used in Renesas .dts(i) files, and that's when all I2C nodes were
> already present in .dtsi in enabled state.

Regarding "disabled", using that in a coherent way probably makes
sense. As for MMC, despite my efforts the DT binding development
turned out far from perfect. So during that time the good ideas
proposed may have accidentally been shot down together with the rest,
my apologies for that.

Now, would it be possible to make sure that all mach-shmobile I2C
descriptions follow the same style? I would like the SoCs to be
supported in the same way, not randomly - both then it comes to
compatbile string format and if "disabled" is used or not.

>> Also, I mentioned this 25 times before already so once more cannot
>> hurt: "renesas,i2c-rcar-h2" needs to be replaced with something more
>> standard.
>
> I didn't count, but yes, it has been discussed and that's been fixed in v2
> of my i2c patches. Now that I've got comments to the ARM patches I can
> also update them with a correct compatibility string.

Good, thanks.

/ magnus
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 885f9f4..a5021112 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -127,6 +127,42 @@ 
 		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>;
 	};
 
+	i2c0: i2c@e6508000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-rcar-h2";
+		reg = <0 0xe6508000 0 0x40>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 287 0x4>;
+	};
+
+	i2c1: i2c@e6518000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-rcar-h2";
+		reg = <0 0xe6518000 0 0x40>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 288 0x4>;
+	};
+
+	i2c2: i2c@e6530000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-rcar-h2";
+		reg = <0 0xe6530000 0 0x40>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 286 0x4>;
+	};
+
+	i2c3: i2c@e6540000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-rcar-h2";
+		reg = <0 0xe6540000 0 0x40>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 290 0x4>;
+	};
+
 	mmcif0: mmcif@ee200000 {
 		compatible = "renesas,sh-mmcif";
 		reg = <0 0xee200000 0 0x80>;
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index fc36d3d..8e5e90b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -52,6 +52,7 @@ 
 #define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
 #define SMSTPCR8 0xe6150990
+#define SMSTPCR9 0xe6150994
 
 #define SDCKCR		0xE6150074
 #define SD2CKCR		0xE6150078
@@ -181,6 +182,7 @@  static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+	MSTP931, MSTP930, MSTP929, MSTP928,
 	MSTP813,
 	MSTP721, MSTP720,
 	MSTP717, MSTP716,
@@ -192,6 +194,10 @@  enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
+	[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
+	[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
+	[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
 	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
@@ -261,6 +267,10 @@  static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
 	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+	CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
+	CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
+	CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
+	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
 	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),