From patchwork Tue Oct 1 18:30:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 2971331 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CD7CA9F245 for ; Tue, 1 Oct 2013 18:31:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 84CB62012E for ; Tue, 1 Oct 2013 18:31:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 26DF8201C0 for ; Tue, 1 Oct 2013 18:30:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751476Ab3JASa6 (ORCPT ); Tue, 1 Oct 2013 14:30:58 -0400 Received: from mail-la0-f41.google.com ([209.85.215.41]:35597 "EHLO mail-la0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751390Ab3JASa6 (ORCPT ); Tue, 1 Oct 2013 14:30:58 -0400 Received: by mail-la0-f41.google.com with SMTP id ec20so6217997lab.14 for ; Tue, 01 Oct 2013 11:30:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YMAdll2mCy8DHtqBuucYbuorIwtjUzJ4Hx/0u8xmGb8=; b=RaiomaFdSgdZptw4K5pNLl8Gta6RUoQwC01L5GuDyXGX2aSkxWm7lv2HTnYhSXhRWz OnGDfr/PBV5gqEKCbl8AxPQ1isck+klDuLmGDS9azwm8H5SjwQ+9BSz4O2JcutVwk4GC u6qUrP54t38INJKQ0YAXwAGIVTyJcU0E++iiIkTOuD/q0TLD05nieOZBArU73MdvQOZT IOxrsL8o1rQRuXXu3e+0lypQRZpi4z2kNXkfEVDBM10LWHnybyBk2pAy1Vl/4Ebcxxdv hZ+wDvWFNy0LEdYGYsB4jhuZ8UAblUPl4Fe9+A82j08h23eyV50GIMEUdRJCIz3BUq3U EtTw== X-Gm-Message-State: ALoCoQkjvDTLShdeSk4Zh+qy51cpPTLSE2aMJFmJthZO+R4UmzIFLOHmHg2OK97Koyw1MZJ3HpSB X-Received: by 10.112.168.35 with SMTP id zt3mr27802404lbb.11.1380652256714; Tue, 01 Oct 2013 11:30:56 -0700 (PDT) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id e4sm4831790lba.15.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 01 Oct 2013 11:30:56 -0700 (PDT) From: Valentine Barshak To: linux-sh@vger.kernel.org Cc: Simon Horman , Magnus Damm , Laurent Pinchart , Guennadi Liakhovetski Subject: [PATCH 2/6] arm: shmobile: lager: Add USBHS support Date: Tue, 1 Oct 2013 22:30:47 +0400 Message-Id: <1380652251-8143-3-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1380652251-8143-1-git-send-email-valentine.barshak@cogentembedded.com> References: <1380652251-8143-1-git-send-email-valentine.barshak@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds USBHS phy control callbacks to the Lager board and registers USBHS device if the driver is enabled. Signed-off-by: Valentine Barshak --- arch/arm/mach-shmobile/board-lager.c | 142 +++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index a8d3ce6..e408fc7 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -34,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -165,6 +167,142 @@ static const struct resource ether_resources[] __initconst = { DEFINE_RES_IRQ(gic_spi(162)), }; +/* USBHS */ +#if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) +static const struct resource usbhs_resources[] __initconst = { + DEFINE_RES_MEM(0xe6590000, 0x200), + DEFINE_RES_IRQ(gic_spi(107)), +}; + +/* USBHS registers */ +#define USBHS_LPSTS_REG 0x102 +#define USBHS_LPSTS_SUSPM (1 << 14) + +#define USBHS_UGCTRL_REG 0x180 +#define USBHS_UGCTRL_CONNECT (1 << 2) +#define USBHS_UGCTRL_PLLRESET (1 << 0) + +#define USBHS_UGCTRL2_REG 0x184 +#define USBHS_UGCTRL2_USB0_PCI (1 << 4) +#define USBHS_UGCTRL2_USB0_HS (3 << 4) +#define USBHS_UGCTRL2_USB2_PCI (0 << 31) +#define USBHS_UGCTRL2_USB2_SS (1 << 31) + +#define USBHS_UGSTS_REG 0x190 +#define USBHS_UGSTS_LOCK (3 << 0) + +struct usbhs_private { + struct renesas_usbhs_platform_info info; + struct platform_device *pdev; + struct clk *clk; +}; + +#define usbhs_get_priv(pdev) \ + container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info) + +static int usbhs_power_on(void __iomem *base) +{ + u32 val; + + val = ioread32(base + USBHS_UGCTRL_REG) & ~USBHS_UGCTRL_PLLRESET; + iowrite32(val, base + USBHS_UGCTRL_REG); + + val = ioread16(base + USBHS_LPSTS_REG) | USBHS_LPSTS_SUSPM; + iowrite16(val, base + USBHS_LPSTS_REG); + + /* + * The manual suggests to check PLL lock status in the UGSTS + * register before enabling connect, however, it is always 0. + */ + val = ioread32(base + USBHS_UGCTRL_REG) | USBHS_UGCTRL_CONNECT; + iowrite32(val, base + USBHS_UGCTRL_REG); + return 0; +} + +static int usbhs_power_off(void __iomem *base) +{ + u32 val; + + val = ioread32(base + USBHS_UGCTRL_REG) & ~USBHS_UGCTRL_CONNECT; + iowrite32(val, base + USBHS_UGCTRL_REG); + + val = ioread16(base + USBHS_LPSTS_REG) & ~USBHS_LPSTS_SUSPM; + iowrite16(val, base + USBHS_LPSTS_REG); + + val = ioread32(base + USBHS_UGCTRL_REG) | USBHS_UGCTRL_PLLRESET; + iowrite32(val, base + USBHS_UGCTRL_REG); + return 0; +} + +static int usbhs_power_ctrl(struct platform_device *pdev, + void __iomem *base, int enable) +{ + if (enable) + return usbhs_power_on(base); + + return usbhs_power_off(base); +} + +static int usbhs_get_id(struct platform_device *pdev) +{ + return USBHS_GADGET; +} + +static int usbhs_hardware_init(struct platform_device *pdev) +{ + struct usbhs_private *priv = usbhs_get_priv(pdev); + struct clk *clk; + + clk = clk_get(NULL, "hsusb"); + if (IS_ERR(clk)) + return -ENODEV; + + /* Enable clocks */ + clk_enable(clk); + priv->clk = clk; + priv->pdev = pdev; + return 0; +} + +static int usbhs_hardware_exit(struct platform_device *pdev) +{ + struct usbhs_private *priv = usbhs_get_priv(pdev); + + if (!priv->clk) + return 0; + + /* Disable clocks */ + clk_disable(priv->clk); + clk_put(priv->clk); + priv->clk = NULL; + return 0; +} + +static struct usbhs_private usbhs_priv __initdata = { + .info = { + .platform_callback = { + .power_ctrl = usbhs_power_ctrl, + .get_id = usbhs_get_id, + .hardware_init = usbhs_hardware_init, + .hardware_exit = usbhs_hardware_exit, + }, + .driver_param = { + .buswait_bwait = 4, + }, + }, +}; + +#define lager_register_usbhs() \ + platform_device_register_resndata(&platform_bus, \ + "renesas_usbhs", -1, \ + usbhs_resources, \ + ARRAY_SIZE(usbhs_resources), \ + &usbhs_priv.info, \ + sizeof(usbhs_priv.info)) +#else /* CONFIG_USB_RENESAS_USBHS_UDC */ +#define lager_register_usbhs() +#endif /* CONFIG_USB_RENESAS_USBHS_UDC */ + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -193,6 +331,9 @@ static const struct pinctrl_map lager_pinctrl_map[] = { "eth_rmii", "eth"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "intc_irq0", "intc"), + /* USB0 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + "usb0", "usb0"), }; static void __init lager_add_standard_devices(void) @@ -222,6 +363,7 @@ static void __init lager_add_standard_devices(void) ðer_pdata, sizeof(ether_pdata)); lager_add_du_device(); + lager_register_usbhs(); } /*