From patchwork Tue Oct 1 18:30:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 2971351 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5D57D9F245 for ; Tue, 1 Oct 2013 18:31:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 429B0201B4 for ; Tue, 1 Oct 2013 18:31:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 195CA201BE for ; Tue, 1 Oct 2013 18:31:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751518Ab3JASbD (ORCPT ); Tue, 1 Oct 2013 14:31:03 -0400 Received: from mail-lb0-f170.google.com ([209.85.217.170]:34601 "EHLO mail-lb0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751479Ab3JASbC (ORCPT ); Tue, 1 Oct 2013 14:31:02 -0400 Received: by mail-lb0-f170.google.com with SMTP id w7so6294172lbi.29 for ; Tue, 01 Oct 2013 11:31:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BzZJPsmAfCveLC3dMUdTkV3Ay+LcnEXiXOAjylOWIlM=; b=aMUPoLFtXdcrPB8OHPlxS9bqM2bzwYFX55Gz+lj3s6ZlEv/itm27MBt3w5ow9UOAyz vWyWsONt+sPLX786bKbHQRNnMe2crMTYuxFnOzqz4qaYrt/lEkaCPnbWI6+R4eos/Czz V1BwDir1mJ+q7JvcrGz36ktNMmojf1F8PPrQEB0JN1D3q2ZdYuNTuWteZzJ6xXJJfby+ vWctwjPWD5IYWoE41dwj4MeowSxJVBb4pZdoRTijvhpFi3xqcSnzg+s9HpUyjn+yrU9w u2pfNmHkV5FXX4U2Oyw/VS3MKVXnX39pBc7SzNlO506wJjJs24HX2hTao4xrcx9WYAKK kPUw== X-Gm-Message-State: ALoCoQm11rP2hhAUTI2zZw2w9tKG9p3l1Xz97U9k9bnYYAyreEqc0okAws3EvlrT7/Y310OdqIW6 X-Received: by 10.112.159.166 with SMTP id xd6mr28196825lbb.22.1380652260511; Tue, 01 Oct 2013 11:31:00 -0700 (PDT) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id e4sm4831790lba.15.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 01 Oct 2013 11:30:59 -0700 (PDT) From: Valentine Barshak To: linux-sh@vger.kernel.org Cc: Simon Horman , Magnus Damm , Laurent Pinchart , Guennadi Liakhovetski Subject: [PATCH 5/6] arm: shmobile: lager: Add internal PCI support Date: Tue, 1 Oct 2013 22:30:50 +0400 Message-Id: <1380652251-8143-6-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1380652251-8143-1-git-send-email-valentine.barshak@cogentembedded.com> References: <1380652251-8143-1-git-send-email-valentine.barshak@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds internal PCI/USB host support to Lager board. There are 3 internal PCI bus controllers with only a EHCI/OHCI device present on each one. This gives us 3 USB host channels. Channel 0 is shared with the USBHS function module. Channel 2 is shared with the USBSS (XHCI) device. Currently no channel configuration is supported, and the default settings are assumed: Channel 0 - USBHS Channel 1 - PCI/USB host Channel 2 - PCI/USB host Signed-off-by: Valentine Barshak --- arch/arm/mach-shmobile/board-lager.c | 41 +++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index e408fc7..08236fb 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -303,6 +303,38 @@ static struct usbhs_private usbhs_priv __initdata = { #define lager_register_usbhs() #endif /* CONFIG_USB_RENESAS_USBHS_UDC */ +/* + * Internal PCI + * There are 3 internal PCI bus controllers with only a EHCI/OHCI + * device present on each one. This gives us 3 USB host channels. + * Channel 0 is shared with the USBHS function module. + * Channel 2 is shared with the USBSS (XHCI) device. + */ +#if IS_ENABLED(CONFIG_PCI) +static const struct resource pci_resources[] __initconst = { + /* Internal PCI0 */ + DEFINE_RES_MEM_NAMED(0xee080000, 0x10000, "PCI0 MEM"), + DEFINE_RES_MEM_NAMED(0xee090000, 0x10000, "PCI0 CFG"), + DEFINE_RES_IRQ(gic_spi(108)), + /* Internal PCI1 */ + DEFINE_RES_MEM_NAMED(0xee0a0000, 0x10000, "PCI1 MEM"), + DEFINE_RES_MEM_NAMED(0xee0b0000, 0x10000, "PCI1 CFG"), + DEFINE_RES_IRQ(gic_spi(112)), + /* Internal PCI2 */ + DEFINE_RES_MEM_NAMED(0xee0c0000, 0x10000, "PCI2 MEM"), + DEFINE_RES_MEM_NAMED(0xee0d0000, 0x10000, "PCI2 CFG"), + DEFINE_RES_IRQ(gic_spi(113)), +}; + +#define lager_register_pci() \ + platform_device_register_simple("pci-rcar-gen2", \ + -1, pci_resources, \ + ARRAY_SIZE(pci_resources)) +} +#else /* CONFIG_PCI */ +#define lager_register_pci() +#endif /* CONFIG_PCI */ + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -332,8 +364,14 @@ static const struct pinctrl_map lager_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "intc_irq0", "intc"), /* USB0 */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + PIN_MAP_MUX_GROUP_DEFAULT(LAGER_USB0_DEVNAME, "pfc-r8a7790", "usb0", "usb0"), + /* USB1 */ + PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2", "pfc-r8a7790", + "usb1", "usb1"), + /* USB2 */ + PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2", "pfc-r8a7790", + "usb2", "usb2"), }; static void __init lager_add_standard_devices(void) @@ -364,6 +402,7 @@ static void __init lager_add_standard_devices(void) lager_add_du_device(); lager_register_usbhs(); + lager_register_pci(); } /*