From patchwork Fri Oct 18 05:33:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cao Minh Hiep X-Patchwork-Id: 3064661 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 47C679F243 for ; Fri, 18 Oct 2013 05:33:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A8892047C for ; Fri, 18 Oct 2013 05:33:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8644F204D6 for ; Fri, 18 Oct 2013 05:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751185Ab3JRFdI (ORCPT ); Fri, 18 Oct 2013 01:33:08 -0400 Received: from m119.secure.ne.jp ([158.199.161.240]:49318 "HELO m119.secure.ne.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1751188Ab3JRFdG (ORCPT ); Fri, 18 Oct 2013 01:33:06 -0400 Received: (qmail 71334 invoked from network); 18 Oct 2013 14:33:04 +0900 Received: from unknown (HELO localhost) (61.118.107.10) by 0 with SMTP; 18 Oct 2013 14:33:04 +0900 From: Cao Minh Hiep To: linux-sh@vger.kernel.org, horms@verge.net.au Cc: magnus.damm@gmail.com, kuninori.morimoto.gx@renesas.com, yoshihiro.shimoda.uh@renesas.com, cm-hiep@jinso.co.jp Subject: [PATCH 2/2 v2] ARM: shmobile: Lager:add SPI FLASH support on QSPI Date: Fri, 18 Oct 2013 14:33:04 +0900 Message-Id: <1382074384-24975-3-git-send-email-cm-hiep@jinso.co.jp> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1382074384-24975-1-git-send-email-cm-hiep@jinso.co.jp> References: <1382074384-24975-1-git-send-email-cm-hiep@jinso.co.jp> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hiep Cao Minh This patch enables Spansion S25FL512SAGMFIG11 chip on QSPI, Add support for the QSPI interface on Lager. Signed-off-by: Hiep Cao Minh --- arch/arm/mach-shmobile/board-lager.c | 69 ++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 78a31b6..5d69cde 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -39,6 +39,11 @@ #include #include #include +#include +#include +#include +#include +#include /* DU */ static struct rcar_du_encoder_data lager_du_encoders[] = { @@ -165,6 +170,67 @@ static const struct resource ether_resources[] __initconst = { DEFINE_RES_IRQ(gic_spi(162)), }; +/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */ +static struct mtd_partition spi_flash_part[] = { + /* Reserved for user loader program, read-only */ + { + .name = "loader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, + /* Reserved for user program, read-only */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = MTD_WRITEABLE, + }, + /* All else is writable (e.g. JFFS2) */ + { + .name = "flash", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_part, + .nr_parts = ARRAY_SIZE(spi_flash_part), + .type = "s25fl512s", +}; + +static struct rspi_plat_data qspi_pdata = { + .num_chipselect = 1, +}; + +static struct spi_board_info spi_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +/* QSPI resource */ +static struct resource qspi_resources[] __initdata = { + DEFINE_RES_MEM(0xe6b10000, 0x1000), + DEFINE_RES_IRQ(gic_spi(184)), +}; + +void __init r8a7790_add_qspi_device(struct rspi_plat_data *pdata) +{ + platform_device_register_resndata( + &platform_bus, "qspi", 0, + qspi_resources, ARRAY_SIZE(qspi_resources), + pdata, sizeof(*pdata)); +} + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -222,6 +288,9 @@ static void __init lager_add_standard_devices(void) ðer_pdata, sizeof(ether_pdata)); lager_add_du_device(); + + r8a7790_add_qspi_device(&qspi_pdata); + spi_register_board_info(spi_info, ARRAY_SIZE(spi_info)); } /*