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[v2,2/2] ARM: shmobile: r8a7791: Add SSI clocks in device tree

Message ID 1388003675-26554-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive)
State Deferred
Headers show

Commit Message

Laurent Pinchart Dec. 25, 2013, 8:34 p.m. UTC 
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7791.dtsi            | 18 ++++++++++++++++++
 include/dt-bindings/clock/r8a7791-clock.h | 13 +++++++++++++
 2 files changed, 31 insertions(+)
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Patch

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 450fdd1..089838d 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -675,6 +675,24 @@ 
 				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
 				"i2c2", "i2c1", "i2c0";
 		};
+		mstp10_clks: mstp10_clks@e6150998 {
+			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+			clocks = <&p_clk>, <&mstp10_clks 0>, <&mstp10_clks 0>,
+				 <&mstp10_clks 0>, <&mstp10_clks 0>, <&mstp10_clks 0>,
+				 <&mstp10_clks 0>, <&mstp10_clks 0>, <&mstp10_clks 0>,
+				 <&mstp10_clks 0>, <&mstp10_clks 0>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7791_CLK_SSI R8A7791_CLK_SSI9 R8A7791_CLK_SSI8
+				R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
+				R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2
+				R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
+			>;
+			clock-output-names =
+				"ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
+		};
 		mstp11_clks: mstp11_clks@e615099c {
 			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 30f82f2..1c8f00d 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -103,6 +103,19 @@ 
 #define R8A7791_CLK_I2C1		30
 #define R8A7791_CLK_I2C0		31
 
+/* MSTP10 */
+#define R8A7791_CLK_SSI			5
+#define R8A7791_CLK_SSI9		6
+#define R8A7791_CLK_SSI8		7
+#define R8A7791_CLK_SSI7		8
+#define R8A7791_CLK_SSI6		9
+#define R8A7791_CLK_SSI5		10
+#define R8A7791_CLK_SSI4		11
+#define R8A7791_CLK_SSI3		12
+#define R8A7791_CLK_SSI2		13
+#define R8A7791_CLK_SSI1		14
+#define R8A7791_CLK_SSI0		15
+
 /* MSTP11 */
 #define R8A7791_CLK_SCIFA3		6
 #define R8A7791_CLK_SCIFA4		7