From patchwork Thu Feb 20 14:49:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 3687851 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 57C6C9F2EC for ; Thu, 20 Feb 2014 14:54:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 611E920145 for ; Thu, 20 Feb 2014 14:54:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C560D20170 for ; Thu, 20 Feb 2014 14:54:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754278AbaBTOyL (ORCPT ); Thu, 20 Feb 2014 09:54:11 -0500 Received: from michel.telenet-ops.be ([195.130.137.88]:59325 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752357AbaBTOtx (ORCPT ); Thu, 20 Feb 2014 09:49:53 -0500 Received: from ayla.of.borg ([84.193.72.141]) by michel.telenet-ops.be with bizsmtp id Uepp1n00u32ts5g06eppNB; Thu, 20 Feb 2014 15:49:52 +0100 Received: from geert by ayla.of.borg with local (Exim 4.76) (envelope-from ) id 1WGUwf-0005kl-Gf; Thu, 20 Feb 2014 15:49:49 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 04/11] ARM: shmobile: lager legacy: Add MSIOF support Date: Thu, 20 Feb 2014 15:49:32 +0100 Message-Id: <1392907779-22053-5-git-send-email-geert@linux-m68k.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392907779-22053-1-git-send-email-geert@linux-m68k.org> References: <1392907779-22053-1-git-send-email-geert@linux-m68k.org> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add MSIOF resources, platform data, platform device, pinctrl, and SPI child device. - Platform device numbering is 1-based for compatibility with the BSP, as QSPI uses zero. - Only MSIOF1 is in use, and thus registered. Its bus contains a single device (a Renesas R2A11302FT PMIC). Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/board-lager.c | 64 ++++++++++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index f0104bfe544e..6062bcbda366 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -287,6 +288,40 @@ static const struct platform_device_info ether_info __initconst = { .dma_mask = DMA_BIT_MASK(32), }; +/* MSIOF */ +static const struct resource sh_msiof0_resources[] __initconst = { + DEFINE_RES_MEM(0xe6e20000, 0x0064), + DEFINE_RES_IRQ(gic_spi(156)), +}; + +static const struct resource sh_msiof1_resources[] __initconst = { + DEFINE_RES_MEM(0xe6e10000, 0x0064), + DEFINE_RES_IRQ(gic_spi(157)), +}; + +static const struct resource sh_msiof2_resources[] __initconst = { + DEFINE_RES_MEM(0xe6e00000, 0x0064), + DEFINE_RES_IRQ(gic_spi(158)), +}; + +static const struct resource sh_msiof3_resources[] __initconst = { + DEFINE_RES_MEM(0xe6c90000, 0x0064), + DEFINE_RES_IRQ(gic_spi(159)), +}; + +static const struct sh_msiof_spi_info sh_msiof_info __initconst = { + .rx_fifo_override = 256, + .num_chipselect = 1, +}; + +#define r8a7790_register_msiof(idx) \ + platform_device_register_resndata(&platform_bus, \ + "spi_r8a7790_msiof", \ + (idx+1), sh_msiof##idx##_resources, \ + ARRAY_SIZE(sh_msiof##idx##_resources), \ + &sh_msiof_info, \ + sizeof(struct sh_msiof_spi_info)) + /* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */ static struct mtd_partition spi_flash_part[] = { /* Reserved for user loader program, read-only */ @@ -325,12 +360,19 @@ static const struct rspi_plat_data qspi_pdata __initconst = { static const struct spi_board_info spi_info[] __initconst = { { - .modalias = "m25p80", - .platform_data = &spi_flash_data, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 0, - .chip_select = 0, + .modalias = "m25p80", + .platform_data = &spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 0, + .chip_select = 0, + }, { + .modalias = "r2a1130x", + .max_speed_hz = 6000000, + .chip_select = 0, + .bus_num = 2, + .mode = SPI_MODE_3, + .controller_data = (void *)-ENOENT, /* HW controlled CS */ }, }; @@ -703,6 +745,15 @@ static const struct pinctrl_map lager_pinctrl_map[] = { /* I2C2 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790", "i2c2", "i2c2"), + /* MSIOF1 */ + PIN_MAP_MUX_GROUP_DEFAULT("spi_r8a7790_msiof.2", "pfc-r8a7790", + "msiof1_clk", "msiof1"), + PIN_MAP_MUX_GROUP_DEFAULT("spi_r8a7790_msiof.2", "pfc-r8a7790", + "msiof1_sync", "msiof1"), + PIN_MAP_MUX_GROUP_DEFAULT("spi_r8a7790_msiof.2", "pfc-r8a7790", + "msiof1_rx", "msiof1"), + PIN_MAP_MUX_GROUP_DEFAULT("spi_r8a7790_msiof.2", "pfc-r8a7790", + "msiof1_tx", "msiof1"), /* QSPI */ PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790", "qspi_ctrl", "qspi"), @@ -811,6 +862,7 @@ static void __init lager_add_standard_devices(void) qspi_resources, ARRAY_SIZE(qspi_resources), &qspi_pdata, sizeof(qspi_pdata)); + r8a7790_register_msiof(1); spi_register_board_info(spi_info, ARRAY_SIZE(spi_info)); platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,