From patchwork Thu Aug 28 15:11:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 4805401 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 24110C0338 for ; Thu, 28 Aug 2014 15:11:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BF07220123 for ; Thu, 28 Aug 2014 15:11:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B63BD20117 for ; Thu, 28 Aug 2014 15:11:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751111AbaH1PLV (ORCPT ); Thu, 28 Aug 2014 11:11:21 -0400 Received: from mail-la0-f52.google.com ([209.85.215.52]:65051 "EHLO mail-la0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750986AbaH1PLU (ORCPT ); Thu, 28 Aug 2014 11:11:20 -0400 Received: by mail-la0-f52.google.com with SMTP id ty20so1112996lab.25 for ; Thu, 28 Aug 2014 08:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=1e2lsOHo+jBcDSvJpTBt5r/zNnTTTjkW2SalfBaUy0E=; b=fiIXx/3poB4quJkvhTg4u93JQyXF7duQhhSzkGOk3HrPZsw3Nkvsf0FdxjTR784Xvx t5m0u1ITxmHaJsPV+J7XHnr2y4CaSiBdSSO3ZfEVW1iWnGhA2E62J1Rfr63nAyxkrHV/ HZtWy3WnszR6XF7baST8baTuRZM9+GNWQanVytj654DkkGonz5Mc4L26/XRbmGlPSDB1 IZrr3B4sIBce60cuE+58qK6+rjP4lI1NYiXKYo9wA0oA0vlIIwb39oxdpMYM/dWIye6t j1Lav5OHZkQzvosQvRR6t/RslRH1pFSERdjEMSDtPmnxgZx5oD//MEgFKsCIHtWghR5t OioQ== X-Received: by 10.112.184.161 with SMTP id ev1mr4672146lbc.82.1409238677919; Thu, 28 Aug 2014 08:11:17 -0700 (PDT) Received: from groucho.site ([179.43.133.226]) by mx.google.com with ESMTPSA id rl10sm2541086lac.28.2014.08.28.08.11.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Aug 2014 08:11:16 -0700 (PDT) From: Ulrich Hecht To: horms@verge.net.au Cc: linux-sh@vger.kernel.org, mturquette@linaro.org, magnus.damm@gmail.com, Laurent Pinchart , devicetree@vger.kernel.org, Geert Uytterhoeven , Ulrich Hecht , Ulrich Hecht Subject: [PATCH v4] clk: shmobile: div6: support selectable-input clocks Date: Thu, 28 Aug 2014 17:11:11 +0200 Message-Id: <1409238671-30452-1-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 1.8.4.5 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ulrich Hecht Support for setting the parent at initialization time based on the current hardware configuration in DIV6 clocks with selectable parents as found in the r8a73a4, r8a7740, sh73a0, and other SoCs. Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven --- This is v3 plus some style adjustments suggested by Laurent. CU Uli Changes since v3: - note that renesas,src-shift and renesas,src-width depend on each other - clarified description - minor coding style fixes Changes since v2: - add r8a73a4 to bindings - use u32 where appropriate - don't split error message Changes since v1: - make sure unrelated register bits are preserved - use the plural for the clocks property in bindings .../bindings/clock/renesas,cpg-div6-clocks.txt | 12 +++++++- drivers/clk/shmobile/clk-div6.c | 32 ++++++++++++++++++---- 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 952e373..2633ea1 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -7,14 +7,24 @@ to 64. Required Properties: - compatible: Must be one of the following + - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks + - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,sh73a0-div6-clock" for SH73A0 (SH-MobileAG5) DIV6 clocks - "renesas,cpg-div6-clock" for generic DIV6 clocks - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock + - clocks: Reference to the parent clock(s) - #clock-cells: Must be 0 - clock-output-names: The name of the clock as a free-form string +Optional Properties: + + - renesas,src-shift: Bit position of the input clock selector (default: + fixed input clock; requires renesas,src-width) + - renesas,src-width: Bit width of the input clock selector (default: fixed + input clock; requires renesas,src-shift) + Example ------- diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index f065f69..f8b57bf 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -39,8 +39,11 @@ struct div6_clock { static int cpg_div6_clock_enable(struct clk_hw *hw) { struct div6_clock *clock = to_div6_clock(hw); + u32 val; - clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); + val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) + | CPG_DIV6_DIV(clock->div - 1); + clk_writel(val, clock->reg); return 0; } @@ -52,7 +55,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw) /* DIV6 clocks require the divisor field to be non-zero when stopping * the clock. */ - clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK), + clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK, clock->reg); } @@ -94,12 +97,14 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, { struct div6_clock *clock = to_div6_clock(hw); unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); + u32 val; clock->div = div; + val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK; /* Only program the new divisor if the clock isn't stopped. */ - if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP)) - clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); + if (!(val & CPG_DIV6_CKSTP)) + clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); return 0; } @@ -120,6 +125,8 @@ static void __init cpg_div6_clock_init(struct device_node *np) const char *parent_name; const char *name; struct clk *clk; + u32 src_shift; + u32 src_width; int ret; clock = kzalloc(sizeof(*clock), GFP_KERNEL); @@ -150,7 +157,22 @@ static void __init cpg_div6_clock_init(struct device_node *np) goto error; } - parent_name = of_clk_get_parent_name(np, 0); + if (!of_property_read_u32(np, "renesas,src-shift", &src_shift)) { + if (!of_property_read_u32(np, "renesas,src-width", + &src_width)) { + unsigned int parent_idx = + (clk_readl(clock->reg) >> src_shift) & + (BIT(src_width) - 1); + parent_name = of_clk_get_parent_name(np, parent_idx); + } else { + pr_err("%s: renesas,src-shift without renesas,src-width in %s\n", + __func__, np->name); + goto error; + } + } else { + parent_name = of_clk_get_parent_name(np, 0); + } + if (parent_name == NULL) { pr_err("%s: failed to get %s DIV6 clock parent name\n", __func__, np->name);