| Message ID | 1414622133-27247-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | Deferred |
| Headers | show |
On Thu, Oct 30, 2014 at 12:35:33AM +0200, Laurent Pinchart wrote: > The renesas,clock-indices property got standardized, replace it with > clock-indices. > > The MSTP clock driver supports both the old and new properties. > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> I believe this duplicates a series which Geert sent recently. > --- > arch/arm/boot/dts/r8a7740.dtsi | 10 +++++----- > arch/arm/boot/dts/r8a7779.dtsi | 6 +++--- > arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++++-------- > arch/arm/boot/dts/r8a7791.dtsi | 18 +++++++++--------- > arch/arm/boot/dts/r8a7794.dtsi | 14 +++++++------- > 5 files changed, 32 insertions(+), 32 deletions(-) > > Simon, can you please take this in your tree for v3.19 ? > > diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi > index aec8da89ef9a..62f6de252d09 100644 > --- a/arch/arm/boot/dts/r8a7740.dtsi > +++ b/arch/arm/boot/dts/r8a7740.dtsi > @@ -453,7 +453,7 @@ > reg = <0xe6150080 4>; > clocks = <&sub_clk>, <&sub_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 > >; > clock-output-names = > @@ -468,7 +468,7 @@ > <&sub_clk>, <&sub_clk>, > <&cpg_clocks R8A7740_CLK_B>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 > R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 > R8A7740_CLK_LCDC0 > @@ -489,7 +489,7 @@ > <&sub_clk>, <&sub_clk>, <&sub_clk>, > <&sub_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA > R8A7740_CLK_SCIFA7 > R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 > @@ -518,7 +518,7 @@ > <&cpg_clocks R8A7740_CLK_HP>, > <&cpg_clocks R8A7740_CLK_HP>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 > R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 > R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 > @@ -535,7 +535,7 @@ > <&cpg_clocks R8A7740_CLK_HP>, > <&cpg_clocks R8A7740_CLK_HP>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7740_CLK_USBH R8A7740_CLK_SDHI2 > R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY > >; > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi > index fda814ed191d..551f38379553 100644 > --- a/arch/arm/boot/dts/r8a7779.dtsi > +++ b/arch/arm/boot/dts/r8a7779.dtsi > @@ -483,7 +483,7 @@ > <&cpg_clocks R8A7779_CLK_P>, > <&cpg_clocks R8A7779_CLK_P>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7779_CLK_HSPI R8A7779_CLK_TMU2 > R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 > R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 > @@ -514,7 +514,7 @@ > <&cpg_clocks R8A7779_CLK_P>, > <&cpg_clocks R8A7779_CLK_S>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7779_CLK_USB01 R8A7779_CLK_USB2 > R8A7779_CLK_DU R8A7779_CLK_VIN2 > R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 > @@ -535,7 +535,7 @@ > clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, > <&s4_clk>, <&s4_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 > R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 > R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 > diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi > index 0f18db0319af..499dfb05a760 100644 > --- a/arch/arm/boot/dts/r8a7790.dtsi > +++ b/arch/arm/boot/dts/r8a7790.dtsi > @@ -994,7 +994,7 @@ > reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; > clocks = <&mp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = <R8A7790_CLK_MSIOF0>; > + clock-indices = <R8A7790_CLK_MSIOF0>; > clock-output-names = "msiof0"; > }; > mstp1_clks: mstp1_clks@e6150134 { > @@ -1005,7 +1005,7 @@ > <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, > <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 > R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 > R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC > @@ -1027,7 +1027,7 @@ > <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, > <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 > R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 > R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 > @@ -1045,7 +1045,7 @@ > <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, > <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 > R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 > R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 > @@ -1060,7 +1060,7 @@ > reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; > clocks = <&extal_clk>, <&p_clk>; > #clock-cells = <1>; > - renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; > + clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; > clock-output-names = "thermal", "pwm"; > }; > mstp7_clks: mstp7_clks@e615014c { > @@ -1070,7 +1070,7 @@ > <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, > <&zx_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 > R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 > R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 > @@ -1086,7 +1086,7 @@ > clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, > <&zs_clk>, <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 > R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 > R8A7790_CLK_SATA0 > @@ -1102,7 +1102,7 @@ > <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, > <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 > R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 > R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS > diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi > index 73e4c8eb5d8c..41a636167c0e 100644 > --- a/arch/arm/boot/dts/r8a7791.dtsi > +++ b/arch/arm/boot/dts/r8a7791.dtsi > @@ -999,7 +999,7 @@ > reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; > clocks = <&mp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = <R8A7791_CLK_MSIOF0>; > + clock-indices = <R8A7791_CLK_MSIOF0>; > clock-output-names = "msiof0"; > }; > mstp1_clks: mstp1_clks@e6150134 { > @@ -1010,7 +1010,7 @@ > <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, > <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU > R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG > R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 > @@ -1030,7 +1030,7 @@ > <&mp_clk>, <&mp_clk>, <&mp_clk>, > <&zs_clk>, <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 > R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 > R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 > @@ -1047,7 +1047,7 @@ > clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, > <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 > R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 > R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 > @@ -1061,7 +1061,7 @@ > reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; > clocks = <&extal_clk>, <&p_clk>; > #clock-cells = <1>; > - renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; > + clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; > clock-output-names = "thermal", "pwm"; > }; > mstp7_clks: mstp7_clks@e615014c { > @@ -1071,7 +1071,7 @@ > <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, > <&zx_clk>, <&zx_clk>, <&zx_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 > R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 > R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 > @@ -1088,7 +1088,7 @@ > clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, > <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 > R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 > >; > @@ -1104,7 +1104,7 @@ > <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, > <&hp_clk>, <&hp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 > R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 > R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 > @@ -1154,7 +1154,7 @@ > reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; > clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 > >; > clock-output-names = "scifa3", "scifa4", "scifa5"; > diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi > index 088e79c6551c..b9539fea9239 100644 > --- a/arch/arm/boot/dts/r8a7794.dtsi > +++ b/arch/arm/boot/dts/r8a7794.dtsi > @@ -455,7 +455,7 @@ > reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; > clocks = <&mp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = <R8A7794_CLK_MSIOF0>; > + clock-indices = <R8A7794_CLK_MSIOF0>; > clock-output-names = "msiof0"; > }; > mstp1_clks: mstp1_clks@e6150134 { > @@ -465,7 +465,7 @@ > <&cp_clk>, > <&zs_clk>, <&zs_clk>, <&zs_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 > R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 > >; > @@ -478,7 +478,7 @@ > clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, > <&mp_clk>, <&mp_clk>, <&mp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 > R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 > R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 > @@ -492,7 +492,7 @@ > reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; > clocks = <&rclk_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7794_CLK_CMT1 > >; > clock-output-names = > @@ -504,7 +504,7 @@ > clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, > <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 > R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 > R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 > @@ -519,7 +519,7 @@ > reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; > clocks = <&p_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7794_CLK_ETHER > >; > clock-output-names = > @@ -530,7 +530,7 @@ > reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; > clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; > #clock-cells = <1>; > - renesas,clock-indices = < > + clock-indices = < > R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 > >; > clock-output-names = "scifa3", "scifa4", "scifa5"; > -- > 2.0.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-sh" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index aec8da89ef9a..62f6de252d09 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -453,7 +453,7 @@ reg = <0xe6150080 4>; clocks = <&sub_clk>, <&sub_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 >; clock-output-names = @@ -468,7 +468,7 @@ <&sub_clk>, <&sub_clk>, <&cpg_clocks R8A7740_CLK_B>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 R8A7740_CLK_LCDC0 @@ -489,7 +489,7 @@ <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA R8A7740_CLK_SCIFA7 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 @@ -518,7 +518,7 @@ <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 @@ -535,7 +535,7 @@ <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7740_CLK_USBH R8A7740_CLK_SDHI2 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY >; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index fda814ed191d..551f38379553 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -483,7 +483,7 @@ <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7779_CLK_HSPI R8A7779_CLK_TMU2 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 @@ -514,7 +514,7 @@ <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_S>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7779_CLK_USB01 R8A7779_CLK_USB2 R8A7779_CLK_DU R8A7779_CLK_VIN2 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 @@ -535,7 +535,7 @@ clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 0f18db0319af..499dfb05a760 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -994,7 +994,7 @@ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; clocks = <&mp_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7790_CLK_MSIOF0>; + clock-indices = <R8A7790_CLK_MSIOF0>; clock-output-names = "msiof0"; }; mstp1_clks: mstp1_clks@e6150134 { @@ -1005,7 +1005,7 @@ <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC @@ -1027,7 +1027,7 @@ <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 @@ -1045,7 +1045,7 @@ <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 @@ -1060,7 +1060,7 @@ reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; clocks = <&extal_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; + clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; clock-output-names = "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { @@ -1070,7 +1070,7 @@ <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 @@ -1086,7 +1086,7 @@ clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 @@ -1102,7 +1102,7 @@ <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 73e4c8eb5d8c..41a636167c0e 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -999,7 +999,7 @@ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; clocks = <&mp_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7791_CLK_MSIOF0>; + clock-indices = <R8A7791_CLK_MSIOF0>; clock-output-names = "msiof0"; }; mstp1_clks: mstp1_clks@e6150134 { @@ -1010,7 +1010,7 @@ <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 @@ -1030,7 +1030,7 @@ <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 @@ -1047,7 +1047,7 @@ clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 @@ -1061,7 +1061,7 @@ reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; clocks = <&extal_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; + clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; clock-output-names = "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { @@ -1071,7 +1071,7 @@ <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 @@ -1088,7 +1088,7 @@ clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 >; @@ -1104,7 +1104,7 @@ <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 @@ -1154,7 +1154,7 @@ reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 >; clock-output-names = "scifa3", "scifa4", "scifa5"; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 088e79c6551c..b9539fea9239 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -455,7 +455,7 @@ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; clocks = <&mp_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7794_CLK_MSIOF0>; + clock-indices = <R8A7794_CLK_MSIOF0>; clock-output-names = "msiof0"; }; mstp1_clks: mstp1_clks@e6150134 { @@ -465,7 +465,7 @@ <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 >; @@ -478,7 +478,7 @@ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 @@ -492,7 +492,7 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&rclk_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7794_CLK_CMT1 >; clock-output-names = @@ -504,7 +504,7 @@ clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 @@ -519,7 +519,7 @@ reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; clocks = <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7794_CLK_ETHER >; clock-output-names = @@ -530,7 +530,7 @@ reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; - renesas,clock-indices = < + clock-indices = < R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 >; clock-output-names = "scifa3", "scifa4", "scifa5";
The renesas,clock-indices property got standardized, replace it with clock-indices. The MSTP clock driver supports both the old and new properties. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> --- arch/arm/boot/dts/r8a7740.dtsi | 10 +++++----- arch/arm/boot/dts/r8a7779.dtsi | 6 +++--- arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++++-------- arch/arm/boot/dts/r8a7791.dtsi | 18 +++++++++--------- arch/arm/boot/dts/r8a7794.dtsi | 14 +++++++------- 5 files changed, 32 insertions(+), 32 deletions(-) Simon, can you please take this in your tree for v3.19 ?