| Message ID | 1415030496-26054-3-git-send-email-ulrich.hecht+renesas@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
On Mon, Nov 3, 2014 at 5:01 PM, Ulrich Hecht <ulrich.hecht+renesas@gmail.com> wrote: > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt > @@ -7,11 +7,17 @@ to 64. > Required Properties: > > - compatible: Must be one of the following > + - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks > + - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks > - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks > - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks > + - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks > - "renesas,cpg-div6-clock" for generic DIV6 clocks > - reg: Base address and length of the memory resource used by the DIV6 clock > - - clocks: Reference to the parent clock > + - clocks: Reference to the parent clock(s); if there are multiple parent > + clocks, one must be specified for each possible parent clock setting > + in the clock register. Invalid settings must be specified as "<0>". > + Trailing invalid settings may be omitted. Is there a possibility that omitting trailing invalid settings will cause 4 or less entries for a clock with 8 parents? That would change its class, and the corresponding src_width and src_shift. So I'm inclined to say the number of parent clocks must be one of 1, 4, or 8, i.e. no omissions, to remove this ambiguity. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Nov 3, 2014 at 6:24 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Mon, Nov 3, 2014 at 5:01 PM, Ulrich Hecht > <ulrich.hecht+renesas@gmail.com> wrote: [...] >> - - clocks: Reference to the parent clock >> + - clocks: Reference to the parent clock(s); if there are multiple parent >> + clocks, one must be specified for each possible parent clock setting >> + in the clock register. Invalid settings must be specified as "<0>". >> + Trailing invalid settings may be omitted. > > Is there a possibility that omitting trailing invalid settings will cause 4 > or less entries for a clock with 8 parents? That would change its class, > and the corresponding src_width and src_shift. I checked that, and all these clocks actually have more than four possible parents. However, ... > So I'm inclined to say the number of parent clocks must be one of 1, 4, or 8, > i.e. no omissions, to remove this ambiguity. ... considering that we don't know what future SoCs may bring, that indeed looks like the better option to me. CU Uli -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 952e373..750550ca 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -7,11 +7,17 @@ to 64. Required Properties: - compatible: Must be one of the following + - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks + - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - "renesas,cpg-div6-clock" for generic DIV6 clocks - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock + - clocks: Reference to the parent clock(s); if there are multiple parent + clocks, one must be specified for each possible parent clock setting + in the clock register. Invalid settings must be specified as "<0>". + Trailing invalid settings may be omitted. - #clock-cells: Must be 0 - clock-output-names: The name of the clock as a free-form string @@ -19,10 +25,11 @@ Required Properties: Example ------- - sd2_clk: sd2_clk@e6150078 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; + sdhi2_clk: sdhi2_clk@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; + clock-output-names = "sdhi2ck"; };
Describes how to specify the parents for clocks with EXSRC bits. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> --- .../bindings/clock/renesas,cpg-div6-clocks.txt | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-)