From patchwork Tue Nov 11 06:42:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Kaneko X-Patchwork-Id: 5270881 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5E7369F387 for ; Tue, 11 Nov 2014 06:43:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8316E20127 for ; Tue, 11 Nov 2014 06:43:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5A80C200EC for ; Tue, 11 Nov 2014 06:43:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752333AbaKKGno (ORCPT ); Tue, 11 Nov 2014 01:43:44 -0500 Received: from mail-pd0-f174.google.com ([209.85.192.174]:56984 "EHLO mail-pd0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752073AbaKKGno (ORCPT ); Tue, 11 Nov 2014 01:43:44 -0500 Received: by mail-pd0-f174.google.com with SMTP id p10so9516285pdj.33 for ; Mon, 10 Nov 2014 22:43:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=xNyIc2aReoEeYtdXV0k55L6d5sb7pI6/gYXDFmOZtW8=; b=lhh1TwsDIP37r1HTiHvkySygB0pGn4C+mPflgWSU5ouJ9YsDbBfzbFFvp+B7lRUjSZ uRaBkrKOt7oWagD7JNNUEL3XnwVrvB6ExON0okJ6lsdImpN2g2f4ca9nHEZfxNcsDYHV 7MCYBTaX+Wupr8Iz1pGECpXiBYmy3QE8hkSMetFDRkcOofjxx0bb5gM5Gps2DM42yezr /6rtwONJj3Fod0CnfI+1jkz4oBVwoEE311Q2CQQze9pJ9BSRPMQKiQtEzJl9bpAKTHm6 oclLKww/y/CnLjqWCAwMJHXfl7N/uInmzbS9oYvnlA2qtaBXMkp2UbhU+2+GFhvAoyON cODA== X-Received: by 10.70.102.99 with SMTP id fn3mr26694917pdb.52.1415688223648; Mon, 10 Nov 2014 22:43:43 -0800 (PST) Received: from localhost.localdomain (p5095-ipngn6701marunouchi.tokyo.ocn.ne.jp. [153.174.4.95]) by mx.google.com with ESMTPSA id td4sm18302818pbc.36.2014.11.10.22.43.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Nov 2014 22:43:43 -0800 (PST) From: Yoshihiro Kaneko To: linux-mmc@vger.kernel.org Cc: Chris Ball , Ulf Hansson , Simon Horman , Magnus Damm , Kuninori Morimoto , linux-sh@vger.kernel.org Subject: [PATCH/RFC] mmc: sh_mmcif: Increase MMCIF clock rate to 97.5MHz Date: Tue, 11 Nov 2014 15:42:22 +0900 Message-Id: <1415688142-20023-1-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shinobu Uehara Signed-off-by: Shinobu Uehara Signed-off-by: Yoshihiro Kaneko --- This patch is based on mmc-next branch of Chris Ball's mmc tree. drivers/mmc/host/sh_mmcif.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 656fbba..fe9a8b7 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -1,6 +1,7 @@ /* * MMCIF eMMC driver. * + * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2010 Renesas Solutions Corp. * Yusuke Goda * @@ -57,6 +58,7 @@ #include #include #include +#include #include #include #include @@ -1371,6 +1373,8 @@ static int sh_mmcif_probe(struct platform_device *pdev) struct resource *res; void __iomem *reg; const char *name; + struct device_node *np = pdev->dev.of_node; + int clk_rate; irq[0] = platform_get_irq(pdev, 0); irq[1] = platform_get_irq(pdev, 1); @@ -1433,6 +1437,16 @@ static int sh_mmcif_probe(struct platform_device *pdev) dev_err(&pdev->dev, "cannot get clock: %d\n", ret); goto eclkget; } + + if (np && !of_property_read_u32(np, "renesas,clk-rate", &clk_rate)) { + if (clk_rate) { + ret = clk_set_rate(host->hclk, clk_rate); + if (ret < 0) + dev_err(&pdev->dev, + "cannot set clock rate: %d\n", ret); + } + } + ret = sh_mmcif_clk_update(host); if (ret < 0) goto eclkupdate;