From patchwork Mon Dec 15 00:35:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 5489691 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D3F389F1CD for ; Mon, 15 Dec 2014 00:36:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EB704209FF for ; Mon, 15 Dec 2014 00:36:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D671A209FD for ; Mon, 15 Dec 2014 00:36:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751286AbaLOAgM (ORCPT ); Sun, 14 Dec 2014 19:36:12 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:41919 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750918AbaLOAgM (ORCPT ); Sun, 14 Dec 2014 19:36:12 -0500 Received: from ayumi.isobedori.kobe.vergenet.net (p4076-ipbfp703kobeminato.hyogo.ocn.ne.jp [122.20.17.76]) by kirsty.vergenet.net (Postfix) with ESMTP id B57F425BEE4; Mon, 15 Dec 2014 11:36:10 +1100 (EST) Received: by ayumi.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id 4709FEDEC59; Mon, 15 Dec 2014 09:36:04 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH v2] ARM: shmobile: r8a7794: Add I2C clocks to device tree Date: Mon, 15 Dec 2014 09:35:50 +0900 Message-Id: <1418603750-9771-1-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.3 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Koji Matsuoka Signed-off-by: Koji Matsuoka [horms: omitted device nodes and aliases; only add clocks] Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- Based on the renesas-devel-20141212-v3.18 tag of my renesas tree v2 [Simon Horman] * Trimmed trailing garbage from changelog v1 [Simon Horman] * Removed portion of patch which adds device nodes and aliases * Renamed patch from "ARM: shmobile: r8a7794: Add I2C driver to device tree" to "ARM: shmobile: r8a7794: Add I2C clocks to device tree" --- arch/arm/boot/dts/r8a7794.dtsi | 12 +++++++++--- include/dt-bindings/clock/r8a7794-clock.h | 6 ++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 068ca09..728d719 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -538,10 +538,16 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cpg_clocks R8A7794_CLK_QSPI>; + clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; - clock-indices = ; - clock-output-names = "qspi_mod"; + clock-indices = < + R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 + R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1 + R8A7794_CLK_I2C0 + >; + clock-output-names = + "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index fba89a4..94d9618 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -87,6 +87,12 @@ #define R8A7794_CLK_GPIO1 11 #define R8A7794_CLK_GPIO0 12 #define R8A7794_CLK_QSPI_MOD 17 +#define R8A7794_CLK_I2C5 25 +#define R8A7794_CLK_I2C4 27 +#define R8A7794_CLK_I2C3 28 +#define R8A7794_CLK_I2C2 29 +#define R8A7794_CLK_I2C1 30 +#define R8A7794_CLK_I2C0 31 /* MSTP11 */ #define R8A7794_CLK_SCIFA3 6