From patchwork Fri Dec 19 00:39:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 5516621 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7EBE19F1CD for ; Fri, 19 Dec 2014 00:39:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9C7D3200F4 for ; Fri, 19 Dec 2014 00:39:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AC4DC200F0 for ; Fri, 19 Dec 2014 00:39:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751555AbaLSAjx (ORCPT ); Thu, 18 Dec 2014 19:39:53 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:49863 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751150AbaLSAjw (ORCPT ); Thu, 18 Dec 2014 19:39:52 -0500 Received: from ayumi.isobedori.kobe.vergenet.net (p4076-ipbfp703kobeminato.hyogo.ocn.ne.jp [122.20.17.76]) by kirsty.vergenet.net (Postfix) with ESMTP id 36757266CED; Fri, 19 Dec 2014 11:39:51 +1100 (EST) Received: by ayumi.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id B5CBAEDEC78; Fri, 19 Dec 2014 09:39:49 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH/RFC] ARM: shmobile: r8a7794: Add Audio DMAC, PWM and Thermal clocks to device tree Date: Fri, 19 Dec 2014 09:39:33 +0900 Message-Id: <1418949573-24211-1-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.3 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is based on the MSTP5 clocks in the r8a7791 device tree. The main difference being that the r8a7794 does not have an Audio DMAC1 clock. Signed-off-by: Simon Horman --- Based on the renesas-devel-20141217-v3.18 tag of my renesas tree. N.B: The R-Car Gen2 v1.8.0 BSP uses zs_clk whereas this patch uses hp_clk as the parent clock for the Audio DMAC clock. In that regard this patch follows the pattern used in mainline for the r8a7790 and r8a7791 SoCs. The BSP's parent clock is consistent for the r8a7790, r8a7791, r8a7793 and r8a7794 SoCs. Support for the r8a7793 SoC is not present in mainline. --- arch/arm/boot/dts/r8a7794.dtsi | 11 +++++++++++ include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 063bf56..7a03166 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -530,6 +530,17 @@ "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&hp_clk>, <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7794_CLK_AUDIO_DMAC0 + R8A7794_CLK_THERMAL R8A7794_CLK_PWM + >; + clock-output-names = "audmac0", "thermal", "pwm"; + }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index d5cfe62..58fa44d 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -61,6 +61,7 @@ #define R8A7794_CLK_USBDMAC1 31 /* MSTP5 */ +#define R8A7794_CLK_AUDIO_DMAC0 2 #define R8A7794_CLK_THERMAL 22 #define R8A7794_CLK_PWM 23