From patchwork Wed Jan 14 11:12:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 5630151 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E37109F357 for ; Wed, 14 Jan 2015 11:13:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 23A2520145 for ; Wed, 14 Jan 2015 11:13:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3EB322038D for ; Wed, 14 Jan 2015 11:13:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751850AbbANLNO (ORCPT ); Wed, 14 Jan 2015 06:13:14 -0500 Received: from xavier.telenet-ops.be ([195.130.132.52]:35595 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751318AbbANLNL (ORCPT ); Wed, 14 Jan 2015 06:13:11 -0500 Received: from ayla.of.borg ([84.193.93.87]) by xavier.telenet-ops.be with bizsmtp id fnD81p00G1t5w8s01nD8Se; Wed, 14 Jan 2015 12:13:09 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1YBLsq-0002a4-2U; Wed, 14 Jan 2015 12:13:08 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1YBLst-00048w-UD; Wed, 14 Jan 2015 12:13:11 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: linux-sh@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/4] ARM: shmobile: Add DT bindings for Renesas memory controllers Date: Wed, 14 Jan 2015 12:12:59 +0100 Message-Id: <1421233982-15883-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1421233982-15883-1-git-send-email-geert+renesas@glider.be> References: <1421233982-15883-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers. Currently memory controller device nodes are used only to reference PM domains, and prevent these PM domains from being powered down, which would crash the system. Signed-off-by: Geert Uytterhoeven --- .../renesas-memory-controllers.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt new file mode 100644 index 0000000000000000..c64b7925cd0924e8 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt @@ -0,0 +1,44 @@ +DT bindings for Renesas R-Mobile and SH-Mobile memory controllers +================================================================= + +Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers. +These memory controllers differ from one SoC variant to another, and are called +by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller +(DBSC3)", "SDRAM Bus State Controller (SBSC)"). + +Currently memory controller device nodes are used only to reference PM +domains, and prevent these PM domains from being powered down, which would +crash the system. + +As there exist no actual drivers for these controllers yet, these bindings +should be considered EXPERIMENTAL for now. + +Required properties: + - compatible: Must be one of the following SoC-specific values: + - "renesas,dbsc-r8a73a4" (R-Mobile APE6) + - "renesas,dbsc3-r8a7740" (R-Mobile A1) + - "renesas,sbsc-sh73a0" (SH-Mobile AG5) + - reg: Must contain the base address and length of the memory controller's + registers. + +Optional properties: + - interrupts: Must contain a list of interrupt specifiers for memory + controller interrupts, if available. + - interrupts-names: Must contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Valid interrupt names are: + - "sec" (secure interrupt) + - "temp" (normal (temperature) interrupt) + - power-domains: Must contain a reference to the PM domain that the memory + controller belongs to, if available. + +Example: + + sbsc1: memory-controller@fe400000 { + compatible = "renesas,sbsc-sh73a0"; + reg = <0xfe400000 0x400>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; + };