| Message ID | 1422348356-18675-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | a895b7cda38cd2fa155be22b531d164f17ec84ec |
| Delegated to: | Simon Horman |
| Headers | show |
On Tue, Jan 27, 2015 at 9:45 AM, Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> wrote: > Enable the ethernet controller for the Alt board. Pin muxing entries are > currently left out as r8a7794 pin control support isn't available yet. > We thus rely on the boot loader to configure ethernet pins for now. > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Looks OK (I don't have an Alt, nor schematics). Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Geert, Thank you for the review. On Tuesday 27 January 2015 09:53:25 Geert Uytterhoeven wrote: > On Tue, Jan 27, 2015 at 9:45 AM, Laurent Pinchart wrote: > > Enable the ethernet controller for the Alt board. Pin muxing entries are > > currently left out as r8a7794 pin control support isn't available yet. > > We thus rely on the boot loader to configure ethernet pins for now. > > > > Signed-off-by: Laurent Pinchart > > <laurent.pinchart+renesas@ideasonboard.com> > > Looks OK (I don't have an Alt, nor schematics). I only have a block diagram, no detailed schematics. I have however successfully tested the patch on Magnus' Alt board. It might depends on particular DIP switch settings, but it should be good enough to start with. > Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
On Tue, Jan 27, 2015 at 10:55:22AM +0200, Laurent Pinchart wrote: > Hi Geert, > > Thank you for the review. > > On Tuesday 27 January 2015 09:53:25 Geert Uytterhoeven wrote: > > On Tue, Jan 27, 2015 at 9:45 AM, Laurent Pinchart wrote: > > > Enable the ethernet controller for the Alt board. Pin muxing entries are > > > currently left out as r8a7794 pin control support isn't available yet. > > > We thus rely on the boot loader to configure ethernet pins for now. > > > > > > Signed-off-by: Laurent Pinchart > > > <laurent.pinchart+renesas@ideasonboard.com> > > > > Looks OK (I don't have an Alt, nor schematics). > > I only have a block diagram, no detailed schematics. I have however > successfully tested the patch on Magnus' Alt board. It might depends on > particular DIP switch settings, but it should be good enough to start with. > > > Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks, I have queued these up for v3.21. Geert, I took the Ack above to cover both patches in this series which has no cover letter. If that was not your intention please let me know. -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello. On 01/27/2015 11:45 AM, Laurent Pinchart wrote: > Enable the ethernet controller for the Alt board. Pin muxing entries are > currently left out as r8a7794 pin control support isn't available yet. > We thus rely on the boot loader to configure ethernet pins for now. > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > --- > arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts > index 0d848e605071..25bf434433b1 100644 > --- a/arch/arm/boot/dts/r8a7794-alt.dts > +++ b/arch/arm/boot/dts/r8a7794-alt.dts > @@ -43,6 +43,19 @@ > status = "okay"; > }; > > +ðer { > + phy-handle = <&phy1>; > + renesas,ether-link-active-low; > + status = "okay"; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + interrupt-parent = <&irqc0>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. [...] WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sergei, Thank you for the review. On Wednesday 04 February 2015 00:43:25 Sergei Shtylyov wrote: > On 01/27/2015 11:45 AM, Laurent Pinchart wrote: > > Enable the ethernet controller for the Alt board. Pin muxing entries are > > currently left out as r8a7794 pin control support isn't available yet. > > We thus rely on the boot loader to configure ethernet pins for now. > > > > Signed-off-by: Laurent Pinchart > > <laurent.pinchart+renesas@ideasonboard.com> > > --- > > > > arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/arch/arm/boot/dts/r8a7794-alt.dts > > b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 > > 100644 > > --- a/arch/arm/boot/dts/r8a7794-alt.dts > > +++ b/arch/arm/boot/dts/r8a7794-alt.dts > > @@ -43,6 +43,19 @@ > > > > status = "okay"; > > > > }; > > > > +ðer { > > + phy-handle = <&phy1>; > > + renesas,ether-link-active-low; > > + status = "okay"; > > + > > + phy1: ethernet-phy@1 { > > + reg = <1>; > > + interrupt-parent = <&irqc0>; > > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > > The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. I don't have the complete Alt schematics. I've double-checked the block diagram and it mentions "GP1_24(IRQ)" next to the PHY. This patch is thus incorrect, but where did you find a mention of IRQ8 ?
Hello. On 02/04/2015 08:29 PM, Laurent Pinchart wrote: >>> Enable the ethernet controller for the Alt board. Pin muxing entries are >>> currently left out as r8a7794 pin control support isn't available yet. >>> We thus rely on the boot loader to configure ethernet pins for now. >>> Signed-off-by: Laurent Pinchart >>> <laurent.pinchart+renesas@ideasonboard.com> >>> --- >>> arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ >>> 1 file changed, 13 insertions(+) >>> diff --git a/arch/arm/boot/dts/r8a7794-alt.dts >>> b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 >>> 100644 >>> --- a/arch/arm/boot/dts/r8a7794-alt.dts >>> +++ b/arch/arm/boot/dts/r8a7794-alt.dts >>> @@ -43,6 +43,19 @@ >>> status = "okay"; >>> }; >>> >>> +ðer { >>> + phy-handle = <&phy1>; >>> + renesas,ether-link-active-low; >>> + status = "okay"; >>> + >>> + phy1: ethernet-phy@1 { >>> + reg = <1>; >>> + interrupt-parent = <&irqc0>; >>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. > I don't have the complete Alt schematics. I don't have *any* Alt schematics, only SILK. > I've double-checked the block > diagram and it mentions "GP1_24(IRQ)" GP1_24 is connected to the PHY's RST# pin, according to the hardware manual. Which seems bad to me -- we hardly needed such kind of reset with the device tree. :-/ Hopefully, U-Boot leaves it high... > next to the PHY. This patch is thus > incorrect, but where did you find a mention of IRQ8 ? In the Alt hardware manual, rev. 0.04. :-) WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Feb 4, 2015 at 6:38 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: >> I've double-checked the block >> diagram and it mentions "GP1_24(IRQ)" > > GP1_24 is connected to the PHY's RST# pin, according to the hardware > manual. Which seems bad to me -- we hardly needed such kind of reset with My (I guess the same as Laurent's) diagram says: GP3_22 (RESET) GP1_24 (IRQ) > the device tree. :-/ Hopefully, U-Boot leaves it high... Can we describe that in DT? Not describing everything will bite us one day (cfr. clocks, PM domains, ...) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello. On 02/04/2015 09:12 PM, Geert Uytterhoeven wrote: >>> I've double-checked the block >>> diagram and it mentions "GP1_24(IRQ)" >> GP1_24 is connected to the PHY's RST# pin, according to the hardware >> manual. Which seems bad to me -- we hardly needed such kind of reset with > My (I guess the same as Laurent's) diagram says: > GP3_22 (RESET) > GP1_24 (IRQ) It doesn't make much sense, GP1_24 is not muxed to any IRQ pin... unless the GPIO1 controller is used as an interrupt controller, that is. >> the device tree. :-/ Hopefully, U-Boot leaves it high... > Can we describe that in DT? We can try, probably in the PHY node... but we'd have to add the driver support for it. > Not describing everything will bite us one day (cfr. clocks, PM domains, ...) Sigh... > Gr{oetje,eeting}s, > Geert WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello. On 02/04/2015 08:38 PM, Sergei Shtylyov wrote: >>>> Enable the ethernet controller for the Alt board. Pin muxing entries are >>>> currently left out as r8a7794 pin control support isn't available yet. >>>> We thus rely on the boot loader to configure ethernet pins for now. >>>> Signed-off-by: Laurent Pinchart >>>> <laurent.pinchart+renesas@ideasonboard.com> >>>> --- >>>> arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ >>>> 1 file changed, 13 insertions(+) >>>> diff --git a/arch/arm/boot/dts/r8a7794-alt.dts >>>> b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 >>>> 100644 >>>> --- a/arch/arm/boot/dts/r8a7794-alt.dts >>>> +++ b/arch/arm/boot/dts/r8a7794-alt.dts >>>> @@ -43,6 +43,19 @@ >>>> status = "okay"; >>>> }; >>>> >>>> +ðer { >>>> + phy-handle = <&phy1>; >>>> + renesas,ether-link-active-low; >>>> + status = "okay"; >>>> + >>>> + phy1: ethernet-phy@1 { >>>> + reg = <1>; >>>> + interrupt-parent = <&irqc0>; >>>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. >> I don't have the complete Alt schematics. > I don't have *any* Alt schematics, only SILK. And SILK also has the PHY IRQ connected to IRQ8#. >> I've double-checked the block >> diagram and it mentions "GP1_24(IRQ)" > GP1_24 is connected to the PHY's RST# pin, according to the hardware > manual. Which seems bad to me -- we hardly needed such kind of reset with the > device tree. :-/ Hopefully, U-Boot leaves it high... >> next to the PHY. This patch is thus >> incorrect, but where did you find a mention of IRQ8 ? > In the Alt hardware manual, rev. 0.04. :-) Mentioned in several places there. Probably it makes sense to compare the dates of our documents. The aforementioned manual is dated June 4, 2014. WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sergei, On Wednesday 04 February 2015 22:37:02 Sergei Shtylyov wrote: > Hello. > > On 02/04/2015 08:38 PM, Sergei Shtylyov wrote: > >>>> Enable the ethernet controller for the Alt board. Pin muxing entries > >>>> are currently left out as r8a7794 pin control support isn't available > >>>> yet. We thus rely on the boot loader to configure ethernet pins for > >>>> now. > >>>> > >>>> Signed-off-by: Laurent Pinchart > >>>> <laurent.pinchart+renesas@ideasonboard.com> > >>>> --- > >>>> > >>>> arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ > >>>> 1 file changed, 13 insertions(+) > >>>> > >>>> diff --git a/arch/arm/boot/dts/r8a7794-alt.dts > >>>> b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 > >>>> 100644 > >>>> --- a/arch/arm/boot/dts/r8a7794-alt.dts > >>>> +++ b/arch/arm/boot/dts/r8a7794-alt.dts > >>>> @@ -43,6 +43,19 @@ > >>>> status = "okay"; > >>>> }; > >>>> > >>>> +ðer { > >>>> + phy-handle = <&phy1>; > >>>> + renesas,ether-link-active-low; > >>>> + status = "okay"; > >>>> + > >>>> + phy1: ethernet-phy@1 { > >>>> + reg = <1>; > >>>> + interrupt-parent = <&irqc0>; > >>>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > >>> > >>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. > >> > >> I don't have the complete Alt schematics. > >> > > I don't have *any* Alt schematics, only SILK. > > And SILK also has the PHY IRQ connected to IRQ8#. > > >> I've double-checked the block > >> diagram and it mentions "GP1_24(IRQ)" > >> > > GP1_24 is connected to the PHY's RST# pin, according to the hardware > > manual. Which seems bad to me -- we hardly needed such kind of reset with > > the device tree. :-/ Hopefully, U-Boot leaves it high... > > > >> next to the PHY. This patch is thus > >> incorrect, but where did you find a mention of IRQ8 ? > >> > > In the Alt hardware manual, rev. 0.04. :-) > > Mentioned in several places there. > > Probably it makes sense to compare the dates of our documents. The > aforementioned manual is dated June 4, 2014. The block diagram I have mentions "Rev0.04 Nov 22, 2013", as well as "PRELIMINARY". Let's use IRQ8 then. IRQ0 is clearly wrong anyway, and we can always fix this later if the hardware manual is wrong.
Hello. On 2/5/2015 3:17 PM, Laurent Pinchart wrote: >>>>>> Enable the ethernet controller for the Alt board. Pin muxing entries >>>>>> are currently left out as r8a7794 pin control support isn't available >>>>>> yet. We thus rely on the boot loader to configure ethernet pins for >>>>>> now. >>>>>> Signed-off-by: Laurent Pinchart >>>>>> <laurent.pinchart+renesas@ideasonboard.com> >>>>>> --- >>>>>> arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ >>>>>> 1 file changed, 13 insertions(+) >>>>>> diff --git a/arch/arm/boot/dts/r8a7794-alt.dts >>>>>> b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 >>>>>> 100644 >>>>>> --- a/arch/arm/boot/dts/r8a7794-alt.dts >>>>>> +++ b/arch/arm/boot/dts/r8a7794-alt.dts >>>>>> @@ -43,6 +43,19 @@ >>>>>> status = "okay"; >>>>>> }; >>>>>> >>>>>> +ðer { >>>>>> + phy-handle = <&phy1>; >>>>>> + renesas,ether-link-active-low; >>>>>> + status = "okay"; >>>>>> + >>>>>> + phy1: ethernet-phy@1 { >>>>>> + reg = <1>; >>>>>> + interrupt-parent = <&irqc0>; >>>>>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >>>>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. >>>> I don't have the complete Alt schematics. >>> I don't have *any* Alt schematics, only SILK. >> And SILK also has the PHY IRQ connected to IRQ8#. >>>> I've double-checked the block >>>> diagram and it mentions "GP1_24(IRQ)" >>> GP1_24 is connected to the PHY's RST# pin, according to the hardware >>> manual. Which seems bad to me -- we hardly needed such kind of reset with >>> the device tree. :-/ Hopefully, U-Boot leaves it high... >>>> next to the PHY. This patch is thus >>>> incorrect, but where did you find a mention of IRQ8 ? >>> In the Alt hardware manual, rev. 0.04. :-) >> Mentioned in several places there. >> Probably it makes sense to compare the dates of our documents. The >> aforementioned manual is dated June 4, 2014. > The block diagram I have mentions "Rev0.04 Nov 22, 2013", as well as > "PRELIMINARY". Let's use IRQ8 then. IRQ0 is clearly wrong anyway, and we can > always fix this later if the hardware manual is wrong. Note that the PHY IRQ can be verified by looking at /proc/interrupts. If you e.g. use NFS root with the Ethernet cable already inserted, there should be exactly one interrupt registered, corresponding to the link-up event. I have verified IRQ8# on SILK this way. WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sergei, On Thursday 05 February 2015 15:35:29 Sergei Shtylyov wrote: > On 2/5/2015 3:17 PM, Laurent Pinchart wrote: > >>>>>> Enable the ethernet controller for the Alt board. Pin muxing entries > >>>>>> are currently left out as r8a7794 pin control support isn't available > >>>>>> yet. We thus rely on the boot loader to configure ethernet pins for > >>>>>> now. > >>>>>> > >>>>>> Signed-off-by: Laurent Pinchart > >>>>>> <laurent.pinchart+renesas@ideasonboard.com> > >>>>>> --- > >>>>>> > >>>>>> arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ > >>>>>> 1 file changed, 13 insertions(+) > >>>>>> > >>>>>> diff --git a/arch/arm/boot/dts/r8a7794-alt.dts > >>>>>> b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 > >>>>>> 100644 > >>>>>> --- a/arch/arm/boot/dts/r8a7794-alt.dts > >>>>>> +++ b/arch/arm/boot/dts/r8a7794-alt.dts > >>>>>> @@ -43,6 +43,19 @@ > >>>>>> > >>>>>> status = "okay"; > >>>>>> > >>>>>> }; > >>>>>> > >>>>>> +ðer { > >>>>>> + phy-handle = <&phy1>; > >>>>>> + renesas,ether-link-active-low; > >>>>>> + status = "okay"; > >>>>>> + > >>>>>> + phy1: ethernet-phy@1 { > >>>>>> + reg = <1>; > >>>>>> + interrupt-parent = <&irqc0>; > >>>>>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > >>>>> > >>>>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. > >>>> > >>>> I don't have the complete Alt schematics. > >>> > >>> I don't have *any* Alt schematics, only SILK. > >> > >> And SILK also has the PHY IRQ connected to IRQ8#. > >> > >>>> I've double-checked the block > >>>> diagram and it mentions "GP1_24(IRQ)" > >>> > >>> GP1_24 is connected to the PHY's RST# pin, according to the hardware > >>> manual. Which seems bad to me -- we hardly needed such kind of reset > >>> with the device tree. :-/ Hopefully, U-Boot leaves it high... > >>> > >>>> next to the PHY. This patch is thus > >>>> incorrect, but where did you find a mention of IRQ8 ? > >>> > >>> In the Alt hardware manual, rev. 0.04. :-) > >> > >> Mentioned in several places there. > >> > >> Probably it makes sense to compare the dates of our documents. The > >> aforementioned manual is dated June 4, 2014. > > > > The block diagram I have mentions "Rev0.04 Nov 22, 2013", as well as > > "PRELIMINARY". Let's use IRQ8 then. IRQ0 is clearly wrong anyway, and we > > can always fix this later if the hardware manual is wrong. > > Note that the PHY IRQ can be verified by looking at /proc/interrupts. If > you e.g. use NFS root with the Ethernet cable already inserted, there > should be exactly one interrupt registered, corresponding to the link-up > event. I have verified IRQ8# on SILK this way. I was planning to try that. I only have remote access to the board, requiring a better internet connection than the flaky 3G I have right now. I should be able to perform tests in the next couple of days.
Hi Guys, > -----Original Message----- > From: linux-sh-owner@vger.kernel.org [mailto:linux-sh- > owner@vger.kernel.org] On Behalf Of Laurent Pinchart > Sent: 05 February 2015 12:18 > To: Sergei Shtylyov; linux-sh@vger.kernel.org > Subject: Re: [PATCH 2/2] ARM: shmobile: r8a7794: alt: Enable ethernet > controller > [snip] > > >>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. > > >> > > >> I don't have the complete Alt schematics. > > >> > > > I don't have *any* Alt schematics, only SILK. > > > > And SILK also has the PHY IRQ connected to IRQ8#. > > > > >> I've double-checked the block > > >> diagram and it mentions "GP1_24(IRQ)" > > >> > > > GP1_24 is connected to the PHY's RST# pin, according to the hardware > > > manual. Which seems bad to me -- we hardly needed such kind of reset with > > > the device tree. :-/ Hopefully, U-Boot leaves it high... > > > > > >> next to the PHY. This patch is thus > > >> incorrect, but where did you find a mention of IRQ8 ? > > >> > > > In the Alt hardware manual, rev. 0.04. :-) > > > > Mentioned in several places there. > > > > Probably it makes sense to compare the dates of our documents. The > > aforementioned manual is dated June 4, 2014. > > The block diagram I have mentions "Rev0.04 Nov 22, 2013", as well as > "PRELIMINARY". Let's use IRQ8 then. IRQ0 is clearly wrong anyway, and we can > always fix this later if the hardware manual is wrong. > The Alt schematics I have (rev 0.18 April 24 2014) match what you are saying. RST# on the PHY connected to GP1_24 and INTRP to IRQ8# with pull and pull down resistors as shown in the h/w manual 0.04 Debug Ether block diagram. Cheers Steve -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Stephen, On Monday 09 February 2015 14:36:17 Stephen Lawrence wrote: > On 05 February 2015 12:18 Laurent Pinchart wrote: > > [snip] > > >>>>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. > >>>> > >>>> I don't have the complete Alt schematics. > >>> > >>> I don't have *any* Alt schematics, only SILK. > >> > >> And SILK also has the PHY IRQ connected to IRQ8#. > >> > >>>> I've double-checked the block > >>>> diagram and it mentions "GP1_24(IRQ)" > >>> > >>> GP1_24 is connected to the PHY's RST# pin, according to the hardware > >>> manual. Which seems bad to me -- we hardly needed such kind of reset > >>> with the device tree. :-/ Hopefully, U-Boot leaves it high... > >>> > >>>> next to the PHY. This patch is thus > >>>> incorrect, but where did you find a mention of IRQ8 ? > >>> > >>> In the Alt hardware manual, rev. 0.04. :-) > >> > >> Mentioned in several places there. > >> > >> Probably it makes sense to compare the dates of our documents. The > >> aforementioned manual is dated June 4, 2014. > > > > The block diagram I have mentions "Rev0.04 Nov 22, 2013", as well as > > "PRELIMINARY". Let's use IRQ8 then. IRQ0 is clearly wrong anyway, and we > > can always fix this later if the hardware manual is wrong. > > The Alt schematics I have (rev 0.18 April 24 2014) match what you are > saying. RST# on the PHY connected to GP1_24 and INTRP to IRQ8# with pull > and pull down resistors as shown in the h/w manual 0.04 Debug Ether block > diagram. Thank you for the information. I've been able to test IRQ8 and the PHY generates a single interrupt, as expected. I'll send a v2.
Hello. On 02/09/2015 08:05 PM, Laurent Pinchart wrote: [...] >>>>>>> The hardware manual tells me the PHY uses IRQ8#, not IRQ0#. >>>>>> I don't have the complete Alt schematics. >>>>> I don't have *any* Alt schematics, only SILK. >>>> And SILK also has the PHY IRQ connected to IRQ8#. >>>>>> I've double-checked the block >>>>>> diagram and it mentions "GP1_24(IRQ)" >>>>> GP1_24 is connected to the PHY's RST# pin, according to the hardware >>>>> manual. Which seems bad to me -- we hardly needed such kind of reset >>>>> with the device tree. :-/ Hopefully, U-Boot leaves it high... >>>>>> next to the PHY. This patch is thus >>>>>> incorrect, but where did you find a mention of IRQ8 ? >>>>> In the Alt hardware manual, rev. 0.04. :-) >>>> Mentioned in several places there. >>>> Probably it makes sense to compare the dates of our documents. The >>>> aforementioned manual is dated June 4, 2014. >>> The block diagram I have mentions "Rev0.04 Nov 22, 2013", as well as >>> "PRELIMINARY". Let's use IRQ8 then. IRQ0 is clearly wrong anyway, and we >>> can always fix this later if the hardware manual is wrong. >> The Alt schematics I have (rev 0.18 April 24 2014) match what you are >> saying. RST# on the PHY connected to GP1_24 and INTRP to IRQ8# with pull >> and pull down resistors as shown in the h/w manual 0.04 Debug Ether block >> diagram. > Thank you for the information. > I've been able to test IRQ8 and the PHY generates a single interrupt, as > expected. I'll send a v2. This patch has been long merged already, so you need to send a fixlet instead. WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 0d848e605071..25bf434433b1 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -43,6 +43,19 @@ status = "okay"; }; +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + &scif2 { status = "okay"; };
Enable the ethernet controller for the Alt board. Pin muxing entries are currently left out as r8a7794 pin control support isn't available yet. We thus rely on the boot loader to configure ethernet pins for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> --- arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)