From patchwork Fri Feb 27 17:38:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 5902181 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9A7F3BF440 for ; Fri, 27 Feb 2015 17:38:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC0E22026C for ; Fri, 27 Feb 2015 17:38:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C881320260 for ; Fri, 27 Feb 2015 17:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754766AbbB0RiQ (ORCPT ); Fri, 27 Feb 2015 12:38:16 -0500 Received: from andre.telenet-ops.be ([195.130.132.53]:60819 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754808AbbB0RiL (ORCPT ); Fri, 27 Feb 2015 12:38:11 -0500 Received: from ayla.of.borg ([84.193.93.87]) by andre.telenet-ops.be with bizsmtp id xVe81p01G1t5w8s01Ve8MD; Fri, 27 Feb 2015 18:38:09 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1YROrY-0001cd-IY; Fri, 27 Feb 2015 18:38:08 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1YROrZ-0003Nh-Nh; Fri, 27 Feb 2015 18:38:09 +0100 From: Geert Uytterhoeven To: Laurent Pinchart , Linus Walleij Cc: Magnus Damm , linux-gpio@vger.kernel.org, linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/4] pinctrl: sh-pfc: Do not overwrite bias configuration Date: Fri, 27 Feb 2015 18:38:02 +0100 Message-Id: <1425058685-12956-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425058685-12956-1-git-send-email-geert+renesas@glider.be> References: <1425058685-12956-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After the last user of the in_pd/in_pu bias parameters of the _PCRH() macro was removed in commit 80da8e02d22caaef ("sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support"), bias parameters are supposed to be configured using the generic pinctl mechanism, which calls the .set_bias() method. However, the PORTCR() macro still represents the control register as consisting of two 4-bit fields. Hence the bias configuration in the uppermost 2 bits is always overwritten with zeroes when a pin is configured for GPIO, disabling any previously configured bias. Use the variable config register macro instead, to represent the register as having 4 fields, and to make sure only the input/output control and function fields are touched. This affects R-Mobile APE6 (r8a73a4), R-Mobile A1 (r8a7740), SH-Mobile AP4 (sh7372), and SH-Mobile AG5 (sh73a0). Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart --- Tested on r8a73a4/ape6evm, which requires a pull-up bias for the GPIO switches. --- drivers/pinctrl/sh-pfc/sh_pfc.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index c83728626906c16c..ed5cf4192fa1a2d0 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -302,20 +302,21 @@ struct sh_pfc_soc_info { /* * PORTnCR macro */ -#define _PCRH(in, in_pd, in_pu, out) \ - 0, (out), (in), 0, \ - 0, 0, 0, 0, \ - 0, 0, (in_pd), 0, \ - 0, 0, (in_pu), 0 - #define PORTCR(nr, reg) \ { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ + /* PULMD[1:0], handled by .set_bias() */ \ + 0, 0, 0, 0, \ + /* IE and OE */ \ + 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ + /* SEC, not supported */ \ + 0, 0, \ + /* PTMD[2:0] */ \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 \ + } \ } #endif /* __SH_PFC_H */