From patchwork Wed Mar 18 18:56:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 6043201 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5E5389F314 for ; Wed, 18 Mar 2015 18:56:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93E3D2041D for ; Wed, 18 Mar 2015 18:56:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8895C203EC for ; Wed, 18 Mar 2015 18:56:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933236AbbCRS4F (ORCPT ); Wed, 18 Mar 2015 14:56:05 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:58546 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932630AbbCRS4E (ORCPT ); Wed, 18 Mar 2015 14:56:04 -0400 Received: from ayla.of.borg ([84.193.93.87]) by xavier.telenet-ops.be with bizsmtp id 56w11q0171t5w8s016w1jZ; Wed, 18 Mar 2015 19:56:02 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1YYJ8L-0007uW-Ha; Wed, 18 Mar 2015 19:56:01 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1YYJ8N-000785-5l; Wed, 18 Mar 2015 19:56:03 +0100 From: Geert Uytterhoeven To: Thomas Gleixner , Jason Cooper , Simon Horman , Magnus Damm Cc: linux-sh@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 7/7] ARM: shmobile: r8a7794: Add IRQC clock to device tree Date: Wed, 18 Mar 2015 19:56:01 +0100 Message-Id: <1426704961-27322-8-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426704961-27322-1-git-send-email-geert+renesas@glider.be> References: <1426704961-27322-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Link the external IRQ controller irqc0 to the IRQC module clock, so it can be power managed using that clock. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 9 +++++++++ include/dt-bindings/clock/r8a7794-clock.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7a3ffa51a8bf2c8b..01cf54f70501e8c2 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -105,6 +105,7 @@ <0 15 IRQ_TYPE_LEVEL_HIGH>, <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7794_CLK_IRQC>; }; dmac0: dma-controller@e6700000 { @@ -625,6 +626,14 @@ "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "irqc"; + }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index d63323032d6ef80e..09da38a58776b403 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -60,6 +60,9 @@ #define R8A7794_CLK_USBDMAC0 30 #define R8A7794_CLK_USBDMAC1 31 +/* MSTP4 */ +#define R8A7794_CLK_IRQC 7 + /* MSTP5 */ #define R8A7794_CLK_THERMAL 22 #define R8A7794_CLK_PWM 23