From patchwork Wed Mar 18 19:16:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 6043701 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DACC9BF90F for ; Wed, 18 Mar 2015 19:16:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EF53C20431 for ; Wed, 18 Mar 2015 19:16:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2B4C62043C for ; Wed, 18 Mar 2015 19:16:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933358AbbCRTQT (ORCPT ); Wed, 18 Mar 2015 15:16:19 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:41468 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933386AbbCRTQP (ORCPT ); Wed, 18 Mar 2015 15:16:15 -0400 Received: from ayla.of.borg ([84.193.93.87]) by baptiste.telenet-ops.be with bizsmtp id 57GE1q00l1t5w8s017GEdn; Wed, 18 Mar 2015 20:16:14 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1YYJRu-0007xl-6A; Wed, 18 Mar 2015 20:16:14 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1YYJRv-0007Ni-Qg; Wed, 18 Mar 2015 20:16:15 +0100 From: Geert Uytterhoeven To: Mike Turquette , Stephen Boyd , Simon Horman , Magnus Damm , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org, linux-pm@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 5/5] ARM: shmobile: r8a7794: Add INTC-SYS clock to device tree Date: Wed, 18 Mar 2015 20:16:04 +0100 Message-Id: <1426706164-28309-6-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426706164-28309-1-git-send-email-geert+renesas@glider.be> References: <1426706164-28309-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Link the ARM GIC to the INTC-SYS module clock, so it can be power managed using that clock in the future. Note that currently the GIC driver doesn't support module clocks nor Runtime PM. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 01cf54f70501e8c2..5667d284a3f0af92 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -48,6 +48,7 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>; }; cmt0: timer@ffca0000 { @@ -629,10 +630,10 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>; + clocks = <&cp_clk>, <&zs_clk>; #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc"; + clock-indices = ; + clock-output-names = "irqc", "intc-sys"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 09da38a58776b403..3ea8cea7d3e79d87 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -62,6 +62,7 @@ /* MSTP4 */ #define R8A7794_CLK_IRQC 7 +#define R8A7794_CLK_INTC_SYS 8 /* MSTP5 */ #define R8A7794_CLK_THERMAL 22