From patchwork Thu May 21 10:51:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 6454011 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C3B25C0432 for ; Thu, 21 May 2015 10:51:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 370D92044C for ; Thu, 21 May 2015 10:51:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 95D0E20435 for ; Thu, 21 May 2015 10:51:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754741AbbEUKvM (ORCPT ); Thu, 21 May 2015 06:51:12 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:34697 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754712AbbEUKvI (ORCPT ); Thu, 21 May 2015 06:51:08 -0400 Received: by wicmc15 with SMTP id mc15so8957394wic.1 for ; Thu, 21 May 2015 03:51:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=M4+UR4kdiI69hJwmnamn8+0hI6bH2GCWBqRpby5R+qk=; b=yL3GM9iyOIUI9BvZQX9fOSuJW0E3Dm+bydpZo+7uUzTFya65YA143o1lYUIffZL0ui eM+AFg5b2EzcFqzMsSsBTRTADbuStv9ZHeYzsyG2KdwZ0z8Q+S9aE8JEo+wmT5HjKfSz E4yjagfl2YEmNmL48gED1ttzP+XD9OeS4x0qmMoD5wKY4b1jaN70KRNOr/PL88tupi8c yARyg6Yzcx3gl9szmpb4sQQVGnKwP5ziikPGVaAtV4wEE1cWUdaLH76qsP6q/HSRBOz0 sSstRl4onn1PZIipyTHLCn1ZSe+3NNyob4/apHQMAe/lJ7acjXf4PjzH+lHbv+GCv8Fo W/sA== X-Received: by 10.180.77.34 with SMTP id p2mr5055031wiw.22.1432205466679; Thu, 21 May 2015 03:51:06 -0700 (PDT) Received: from groucho.site (ipbcc02225.dynamic.kabel-deutschland.de. [188.192.34.37]) by mx.google.com with ESMTPSA id g5sm31493120wjq.6.2015.05.21.03.51.05 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 May 2015 03:51:05 -0700 (PDT) From: Ulrich Hecht To: linux-sh@vger.kernel.org Cc: magnus.damm@gmail.com, Ulrich Hecht Subject: [RFC] pinctrl: sh-pfc: add minimal R-Car Gen3 support Date: Thu, 21 May 2015 12:51:03 +0200 Message-Id: <1432205463-9640-1-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 2.3.5 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY,UPPERCASE_50_75 autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi! This is a minimal PFC implementation for Gen3, limited to the bits and pieces related to SCIF0. Considering that there is no hardware and no non-preliminary documentation (at least not with me), this serves more to keep the code from getting lost than as an actual request for comment. :) CU Uli Not-Signed-off-by: Ulrich Hecht --- drivers/pinctrl/sh-pfc/pfc-rcar3.c | 494 +++++++++++++++++++++++++++++++++++++ 1 file changed, 494 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-rcar3.c diff --git a/drivers/pinctrl/sh-pfc/pfc-rcar3.c b/drivers/pinctrl/sh-pfc/pfc-rcar3.c new file mode 100644 index 0000000..b7d0282 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-rcar3.c @@ -0,0 +1,494 @@ +/* + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include +#include + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx), \ + PORT_GP_32(6, fn, sfx), \ + PORT_GP_32(7, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR5 */ + FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4, + FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20, + FN_IP11_24_27, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, + FN_IP12_11_8, FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, + FN_IP12_27_24, FN_MSIOF0_SCK, FN_IP12_31_28, FN_IP13_3_0, + FN_MSIOF0_TXD, FN_IP13_7_4, FN_MSIOF0_RXD, FN_IP13_11_8, + FN_IP13_15_12, FN_IP13_19_16, + + /* IPSR10 */ + FN_SD3_DAT6, FN_SD3_CD, FN_SD3_DAT7, FN_SD3_WP, FN_SCL2_B, + FN_SIM0_RST_A, FN_SD0_CD, FN_SDA2_B, FN_SD0_WP, FN_SIM0_CLK_B, + FN_SD1_CD, FN_SIM0_D_B, FN_SD1_WP, FN_SDA2_A, FN_SIM0_RST_B, + FN_STP_OPWM_0_C, FN_RIF0_CLK_B, FN_SCK0, FN_HSCK1_B, + FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, + FN_RIF0_D0_B, FN_RX0, FN_HRX1_B, + + /* IPSR11 */ + FN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, FN_TS_SCK1_C, + FN_STP_ISCLK1_C, FN_RIF1_CLK_B, FN_RTS1_N_TANS, FN_HRTS1_N_A, + FN_MSIOF1_TXD_B, FN_TS_SDAT1_C, FN_STP_ISD1_C, FN_RIF1_D1_B, + FN_CTS1_N, FN_HCTS1_N_A, FN_MSIOF1_RXD_B, FN_TS_SDEN1_C, + FN_STP_ISEN_1_C, FN_RIF1_D0_B, FN_TX1_A, FN_HTX1_A, FN_TS_SDEN0_C, + FN_STP_ISEN_0_C, FN_RIF1_D0_C, FN_RX1_A, FN_HRX1_A, FN_TS_SDAT0_C, + FN_STP_ISD_0_C, FN_RIF1_CLK_C, FN_RTS0_N_TANS, FN_HRTS1_N_B, + FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, FN_SCL2_A, FN_STP_IVCXO27_1_C, + FN_RIF0_SYNC_B, FN_CTS0_N, FN_HCTS1_N_B, FN_MSIOF1_SYNC_B, + FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, FN_TX0, + FN_HTX1_B, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, + + /* MOD_SEL0 */ + FN_SEL_5LINE_0, FN_SEL_5LINE_1, + + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_ADG_2, FN_SEL_ADG_3, + + FN_SEL_CANFD_0, FN_SEL_CANFD_1, + + FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, + FN_SEL_DRIF0_2, FN_SEL_DRIF0_3, + + FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, + FN_SEL_DRIF1_2, FN_SEL_DRIF1_3, + + FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, + + FN_SEL_FM_0, FN_SEL_FM_1, + + FN_SEL_FSO_0, FN_SEL_FSO_1, + + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + + FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, + FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, + + FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, + + FN_SEL_I2C1_0, FN_SEL_I2C1_1, + + FN_SEL_I2C2_0, FN_SEL_I2C2_1, + + FN_SEL_I2C6_0, FN_SEL_I2C6_1, + FN_SEL_I2C6_2, FN_SEL_I2C6_3, + + FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, + + FN_SEL_LBSC_0, FN_SEL_LBSC_1, + + FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, + FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, + FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, + FN_SEL_MSIOF1_6, FN_SEL_MSIOF1_7, + + FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, + FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, + + FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, + FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, + + /* MOD_SEL1 */ + FN_SEL_PWM1_0, FN_SEL_PWM1_1, + + FN_SEL_PWM2_0, FN_SEL_PWM2_1, + + FN_SEL_PWM3_0, FN_SEL_PWM3_1, + + FN_SEL_PWM4_0, FN_SEL_PWM4_1, + + FN_SEL_PWM5_0, FN_SEL_PWM5_1, + + FN_SEL_PWM6_0, FN_SEL_PWM6_1, + + FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, + + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, + + FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, + + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, + + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + + FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, + + FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, + FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, + + FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, + + FN_SEL_SSI_0, FN_SEL_SSI_1, + + FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, + FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, + FN_SEL_SSP1_0_4, FN_SEL_SSP1_0_5, + FN_SEL_SSP1_0_6, FN_SEL_SSP1_0_7, + + FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1_1, + FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_1_3, + + FN_SEL_TIMER_TMU_0, FN_SEL_TIMER_TMU_1, + + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_TSIF0_4, FN_SEL_TSIF0_5, FN_SEL_TSIF0_6, FN_SEL_TSIF0_7, + + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* IPSR10 */ + SD3_DAT6_MARK, SD3_CD_MARK, SD3_DAT7_MARK, SD3_WP_MARK, SCL2_B_MARK, + SIM0_RST_A_MARK, SD0_CD_MARK, SDA2_B_MARK, SD0_WP_MARK, + SIM0_CLK_B_MARK, SD1_CD_MARK, SIM0_D_B_MARK, SD1_WP_MARK, + SDA2_A_MARK, SIM0_RST_B_MARK, STP_OPWM_0_C_MARK, RIF0_CLK_B_MARK, + SCK0_MARK, HSCK1_B_MARK, MSIOF1_SS2_B_MARK, AUDIO_CLKC_B_MARK, + TS_SCK0_C_MARK, STP_ISCLK_0_C_MARK, RIF0_D0_B_MARK, RX0_MARK, + HRX1_B_MARK, + + /* IPSR11 */ + SCK2_MARK, SCIF_CLK_B_MARK, MSIOF1_SCK_B_MARK, TS_SCK1_C_MARK, + STP_ISCLK1_C_MARK, RIF1_CLK_B_MARK, RTS1_N_TANS_MARK, HRTS1_N_A_MARK, + MSIOF1_TXD_B_MARK, TS_SDAT1_C_MARK, STP_ISD1_C_MARK, RIF1_D1_B_MARK, + CTS1_N_MARK, HCTS1_N_A_MARK, MSIOF1_RXD_B_MARK, TS_SDEN1_C_MARK, + STP_ISEN_1_C_MARK, RIF1_D0_B_MARK, TX1_A_MARK, HTX1_A_MARK, TS_SDEN0_C_MARK, + STP_ISEN_0_C_MARK, RIF1_D0_C_MARK, RX1_A_MARK, HRX1_A_MARK, TS_SDAT0_C_MARK, + STP_ISD_0_C_MARK, RIF1_CLK_C_MARK, RTS0_N_TANS_MARK, HRTS1_N_B_MARK, + MSIOF1_SS1_B_MARK, AUDIO_CLKA_B_MARK, SCL2_A_MARK, STP_IVCXO27_1_C_MARK, + RIF0_SYNC_B_MARK, CTS0_N_MARK, HCTS1_N_B_MARK, MSIOF1_SYNC_B_MARK, + TS_SPSYNC1_C_MARK, STP_ISSYNC_1_C_MARK, RIF1_SYNC_B_MARK, TX0_MARK, + HTX1_B_MARK, TS_SPSYNC0_C_MARK, STP_ISSYNC_0_C_MARK, RIF0_D1_B_MARK, + + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + /* IPSR10 */ + PINMUX_IPSR_DATA(IP10_27_24, SCK0), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, SDA2_A, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), + + PINMUX_IPSR_DATA(IP10_31_28, RX0), + PINMUX_IPSR_MODSEL_DATA(IP10_31_28, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), + + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_3_0, TX0), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), + + PINMUX_IPSR_DATA(IP11_7_4, CTS0_N), + PINMUX_IPSR_MODSEL_DATA(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1), + + PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS), + PINMUX_IPSR_MODSEL_DATA(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_8, SCL2_A, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int scif0_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk_b), +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scif0), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + GP_5_25_FN, FN_IP13_19_16, + GP_5_24_FN, FN_IP13_15_12, + GP_5_23_FN, FN_IP13_11_8, + GP_5_22_FN, FN_MSIOF0_RXD, + GP_5_21_FN, FN_IP13_7_4, + GP_5_20_FN, FN_MSIOF0_TXD, + GP_5_19_FN, FN_IP13_3_0, + GP_5_18_FN, FN_IP12_31_28, + GP_5_17_FN, FN_MSIOF0_SCK, + GP_5_16_FN, FN_IP12_27_24, + GP_5_15_FN, FN_IP12_23_20, + GP_5_14_FN, FN_IP12_19_16, + GP_5_13_FN, FN_IP12_15_12, + GP_5_12_FN, FN_IP12_11_8, + GP_5_11_FN, FN_IP12_7_4, + GP_5_10_FN, FN_IP12_3_0, + GP_5_9_FN, FN_IP11_31_28, + GP_5_8_FN, FN_IP11_24_27, + GP_5_7_FN, FN_IP11_23_20, + GP_5_6_FN, FN_IP11_19_16, + GP_5_5_FN, FN_IP11_15_12, + GP_5_4_FN, FN_IP11_11_8, + GP_5_3_FN, FN_IP11_7_4, + GP_5_2_FN, FN_IP11_3_0, + GP_5_1_FN, FN_IP10_31_28, + GP_5_0_FN, FN_IP10_27_24, } + }, + + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + /* IP10_31_28 */ + FN_RX0, FN_HRX1_B, 0, 0, + 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, + /* IP10_27_24 */ + FN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, + FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B, + /* IP10_23_20 */ + FN_SD1_WP, 0, 0, 0, + 0, FN_SIM0_D_B, 0, 0, + /* IP10_19_16 */ + FN_SD1_CD, 0, 0, 0, + 0, FN_SIM0_CLK_B, 0, 0, + /* IP10_15_12 */ + FN_SD0_WP, 0, 0, 0, + FN_SDA2_B, 0, 0, 0, + /* IP10_11_8 */ + FN_SD0_CD, 0, 0, 0, + FN_SCL2_B, FN_SIM0_RST_A, 0, + /* IP10_7_4 */ + FN_SD3_DAT7, FN_SD3_WP, 0, 0, + 0, 0, 0, 0, + /* IP10_3_0 */ + FN_SD3_DAT6, FN_SD3_CD, 0, 0, + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + /* IP11_31_28 */ + FN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, + 0, FN_TS_SCK1_C, FN_STP_ISCLK1_C, FN_RIF1_CLK_B, + /* IP11_27_24 */ + FN_RTS1_N_TANS, FN_HRTS1_N_A, FN_MSIOF1_TXD_B, 0, + 0, FN_TS_SDAT1_C, FN_STP_ISD1_C, FN_RIF1_D1_B, + /* IP11_23_20 */ + FN_CTS1_N, FN_HCTS1_N_A, FN_MSIOF1_RXD_B, 0, + 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, + /* IP11_19_16 */ + FN_TX1_A, FN_HTX1_A, 0, 0, + 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, + /* IP11_15_12 */ + FN_RX1_A, FN_HRX1_A, 0, 0, + 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, + /* IP11_11_8 */ + FN_RTS0_N_TANS, FN_HRTS1_N_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, + FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, + /* IP11_7_4 */ + FN_CTS0_N, FN_HCTS1_N_B, FN_MSIOF1_SYNC_B, 0, + 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, + /* IP11_3_0 */ + FN_TX0, FN_HTX1_B, 0, 0, + 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, } + }, + + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 1, 2, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 2, + 1, 1, 1, 2, 1, 1, 3, 2, 2, 1) { + FN_SEL_5LINE_0, FN_SEL_5LINE_1, + + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_ADG_2, FN_SEL_ADG_3, + + FN_SEL_CANFD_0, FN_SEL_CANFD_1, + + FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, + FN_SEL_DRIF0_2, FN_SEL_DRIF0_3, + + FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, + FN_SEL_DRIF1_2, FN_SEL_DRIF1_3, + + FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, + + FN_SEL_FM_0, FN_SEL_FM_1, + + FN_SEL_FSO_0, FN_SEL_FSO_1, + + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + + FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, + FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, + + FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, + + FN_SEL_I2C1_0, FN_SEL_I2C1_1, + + FN_SEL_I2C2_0, FN_SEL_I2C2_1, + + FN_SEL_I2C6_0, FN_SEL_I2C6_1, + FN_SEL_I2C6_2, FN_SEL_I2C6_3, + + FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, + + FN_SEL_LBSC_0, FN_SEL_LBSC_1, + + FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, + FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, + FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, + FN_SEL_MSIOF1_6, FN_SEL_MSIOF1_7, + + FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, + FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, + + FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, + FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, + + 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 1, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 2, + 1, 2, 1, 1, 3, 2, 1, 3, 2) { + FN_SEL_PWM1_0, FN_SEL_PWM1_1, + + FN_SEL_PWM2_0, FN_SEL_PWM2_1, + + FN_SEL_PWM3_0, FN_SEL_PWM3_1, + + FN_SEL_PWM4_0, FN_SEL_PWM4_1, + + FN_SEL_PWM5_0, FN_SEL_PWM5_1, + + FN_SEL_PWM6_0, FN_SEL_PWM6_1, + + FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, + + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, + + FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, + + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, + + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + + FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, + + FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, + FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, + + FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, + + FN_SEL_SSI_0, FN_SEL_SSI_1, + + FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, + FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, + FN_SEL_SSP1_0_4, FN_SEL_SSP1_0_5, + FN_SEL_SSP1_0_6, FN_SEL_SSP1_0_7, + + FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1_1, + FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_1_3, + + FN_SEL_TIMER_TMU_0, FN_SEL_TIMER_TMU_1, + + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, + FN_SEL_TSIF0_3, FN_SEL_TSIF0_4, FN_SEL_TSIF0_5, + FN_SEL_TSIF0_6, FN_SEL_TSIF0_7, + + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_TSIF1_3, } + }, + + { }, +}; + +const struct sh_pfc_soc_info rcar3_pinmux_info = { + .name = "rcar3_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +};