From patchwork Thu May 21 10:57:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 6454021 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6A4B7C0432 for ; Thu, 21 May 2015 10:57:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 826712039C for ; Thu, 21 May 2015 10:57:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 957F620251 for ; Thu, 21 May 2015 10:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754470AbbEUK5n (ORCPT ); Thu, 21 May 2015 06:57:43 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:64115 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751722AbbEUK5m (ORCPT ); Thu, 21 May 2015 06:57:42 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie2.idc.renesas.com with ESMTP; 21 May 2015 19:57:40 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 93C144C568; Thu, 21 May 2015 19:57:40 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id 622091806F; Thu, 21 May 2015 19:57:40 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id 5A2F01800A; Thu, 21 May 2015 19:57:40 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac3.idc.renesas.com with ESMTP id VAA14200; Thu, 21 May 2015 19:57:40 +0900 X-IronPort-AV: E=Sophos;i="5.13,468,1427727600"; d="scan'208";a="186681226" Received: from mail-hk1lp0124.outbound.protection.outlook.com (HELO APAC01-HK1-obe.outbound.protection.outlook.com) ([207.46.51.124]) by relmlii1.idc.renesas.com with ESMTP/TLS/AES256-SHA; 21 May 2015 19:57:39 +0900 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=<>; Received: from localhost (211.11.155.147) by SG2PR06MB0919.apcprd06.prod.outlook.com (25.162.204.152) with Microsoft SMTP Server (TLS) id 15.1.166.22; Thu, 21 May 2015 10:57:37 +0000 From: Yoshihiro Shimoda To: , , , , , CC: , , , Yoshihiro Shimoda Subject: [PATCH v4 1/2] pwm: Add device tree binding document for R-Car PWM Timer Date: Thu, 21 May 2015 19:57:25 +0900 Message-ID: <1432205846-4312-2-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 1.9.4.msysgit.1 In-Reply-To: <1432205846-4312-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1432205846-4312-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Originating-IP: [211.11.155.147] X-ClientProxiedBy: KAWPR01CA0017.jpnprd01.prod.outlook.com (25.161.24.27) To SG2PR06MB0919.apcprd06.prod.outlook.com (25.162.204.152) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SG2PR06MB0919; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:SG2PR06MB0919; BCL:0; PCL:0; RULEID:; SRVR:SG2PR06MB0919; X-Forefront-PRVS: 0583A86C08 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6009001)(6069001)(189002)(199003)(46102003)(5001770100001)(47776003)(66066001)(64706001)(575784001)(229853001)(50226001)(68736005)(87976001)(78352002)(48376002)(50466002)(76176999)(50986999)(5001830100001)(36756003)(42382002)(76506005)(5001860100001)(42186005)(62966003)(77156002)(122386002)(5001960100002)(40100003)(107886002)(4001540100001)(81156007)(101416001)(97736004)(92566002)(19580395003)(2950100001)(19580405001)(105586002)(106356001)(189998001)(33646002)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:SG2PR06MB0919; H:localhost; FPR:; SPF:None; PTR:InfoNoRecords; MX:0; A:0; LANG:en; X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2015 10:57:37.8505 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB0919 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add binding document for Renesas PWM Timer on R-Car SoCs. Signed-off-by: Yoshihiro Shimoda Acked-by: Geert Uytterhoeven --- .../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt new file mode 100644 index 0000000..ea0a27b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -0,0 +1,27 @@ +* Renesas R-Car PWM Timer Controller + +Required Properties: +- compatible: should be one of the following. + - "renesas,pwm-rcar": for generic R-Car compatible PWM Timer + - "renesas,pwm-r8a7778": for R-Car M1A + - "renesas,pwm-r8a7779": for R-Car H1 + - "renesas,pwm-r8a7790": for R-Car H2 + - "renesas,pwm-r8a7791": for R-Car M2-W + - "renesas,pwm-r8a7794": for R-Car E2 +- reg: base address and length of the registers block for the PWM. +- #pwm-cells: should be 2. See pwm.txt in this directory for a description of + the cells format. +- clocks: clock phandle and specifier pair. +- pinctrl-0: phandle, referring to a default pin configuration node. +- pinctrl-names: Set to "default". + +Example: R8A7790 (R-Car H2) PWM Timer node + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + clocks = <&mstp5_clks R8A7790_CLK_PWM>; + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + };